# '1'-bit Count-based Sorting Unit to Reduce Link Power in DNN Accelerators

arXiv: https://arxiv.org/abs/2601.14087 · HTML: https://mlsanity.com/paper/2601.14087/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 4 of its 21 references that are in the map.
- First posted on arXiv 20 Jan 2026.

## Builds on (most cited first, 4 of 4)

- [Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey](https://mlsanity.com/paper/2203.08737/) (2022)
- [A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms](https://mlsanity.com/paper/2306.15552/) (2023)
- [Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks](https://mlsanity.com/paper/2107.02358/) (2021)
- [Bit Transition Reduction by Data Transmission Ordering in NoC-based DNN Accelerator](https://mlsanity.com/paper/2509.00500/) (2025)

## Abstract (arXiv)

Interconnect power consumption remains a bottleneck in Deep Neural Network (DNN) accelerators. While ordering data based on '1'-bit counts can mitigate this via reduced switching activity, practical hardware sorting implementations remain underexplored. This work proposes the hardware implementation of a comparison-free sorting unit optimized for Convolutional Neural Networks (CNN). By leveraging approximate computing to group population counts into coarse-grained buckets, our design achieves hardware area reductions while preserving the link power benefits of data reordering. Our approximate sorting unit achieves up to 35.4% area reduction while maintaining 19.50% BT reduction compared to 20.42% of precise implementation.