# PRIMAL: Processing-In-Memory Based Low-Rank Adaptation for LLM Inference Accelerator

arXiv: https://arxiv.org/abs/2601.13628 · HTML: https://mlsanity.com/paper/2601.13628/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 20 Jan 2026.

## Built on by (most cited first, 1 of 1)

- [CHIPSMORE: Compute-in-Interconnect and -Memory Chiplets for Multi-Mode Multi-Request LLM Inference Acceleration](https://mlsanity.com/paper/2608.30509/) (2026)

## Abstract (arXiv)

This paper presents PRIMAL, a processing-in-memory (PIM) based large language model (LLM) inference accelerator with low-rank adaptation (LoRA). PRIMAL integrates heterogeneous PIM processing elements (PEs), interconnected by 2D-mesh inter-PE computational network (IPCN). A novel SRAM reprogramming and power gating (SRPG) scheme enables pipelined LoRA updates and sub-linear power scaling by overlapping reconfiguration with computation and gating idle resources. PRIMAL employs optimized spatial mapping and dataflow orchestration to minimize communication overhead, and achieves 1.5× throughput and 25× energy efficiency over NVIDIA H100 with LoRA rank 8 (Q,V) on Llama-13B.