# LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification

arXiv: https://arxiv.org/abs/2601.02624 · HTML: https://mlsanity.com/paper/2601.02624/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 9 of its 28 references that are in the map.
- First posted on arXiv 6 Jan 2026.

## Builds on (most cited first, 9 of 9)

- [LLM for SoC Security: A Paradigm Shift](https://mlsanity.com/paper/2310.06046/) (2023)
- [ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification](https://mlsanity.com/paper/2505.06821/) (2025)
- [SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models](https://mlsanity.com/paper/2506.20415/) (2025)
- [BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detection](https://mlsanity.com/paper/2505.22878/) (2025)
- [Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA](https://mlsanity.com/paper/2001.09672/) (2020)
- [LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs](https://mlsanity.com/paper/2504.21770/) (2025)
- [Toward Automated Potential Primary Asset Identification in Verilog Designs](https://mlsanity.com/paper/2502.04648/) (2025)
- [High-Level Approaches to Hardware Security: A Tutorial](https://mlsanity.com/paper/2207.10466/) (2022)
- [Information Flow Coverage Metrics for Hardware Security Verification](https://mlsanity.com/paper/2304.08263/) (2023)

## Built on by (most cited first, 1 of 1)

- [VeriChat: An Agentic Conversational AI Assistant for Hardware Security Verification](https://mlsanity.com/paper/2607.01668/) (2026)

## Abstract (arXiv)

The growing complexity of modern system-on-chip (SoC) and IP designs is making security assurance difficult day by day. One of the fundamental steps in the pre-silicon security verification of a hardware design is the identification of security assets, as it substantially influences downstream security verification tasks, such as threat modeling, security property generation, and vulnerability detection. Traditionally, assets are determined manually by security experts, requiring significant time and expertise. To address this challenge, we present LAsset, a novel automated framework that leverages large language models (LLMs) to identify security assets from both hardware design specifications and register-transfer level (RTL) descriptions. The framework performs structural and semantic analysis to identify intra-module primary and secondary assets and derives inter-module relationships to systematically characterize security dependencies at the design level. Experimental results show that the proposed framework achieves high classification accuracy, reaching up to 90% recall rate in SoC design, and 93% recall rate in IP designs. This automation in asset identification significantly reduces manual overhead and supports a scalable path forward for secure hardware development.