# ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction

arXiv: https://arxiv.org/abs/2511.23340 · HTML: https://mlsanity.com/paper/2511.23340/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 15 of its 28 references that are in the map.
- First posted on arXiv 28 Nov 2025.

## Builds on (most cited first, 15 of 15)

- [Graph Attention Networks](https://mlsanity.com/paper/1710.10903/) (2017)
- [A Comprehensive Survey on Graph Neural Networks](https://mlsanity.com/paper/1901.00596/) (2019)
- [Gate-Variants of Gated Recurrent Unit (GRU) Neural Networks](https://mlsanity.com/paper/1701.05923/) (2017)
- [A Random Forest Guided Tour](https://mlsanity.com/paper/1511.05741/) (2015)
- [Machine Learning for Electronic Design Automation: A Survey](https://mlsanity.com/paper/2102.03357/) (2021)
- [Efficient Probabilistic Logic Reasoning with Graph Neural Networks](https://mlsanity.com/paper/2001.11850/) (2020)
- [MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design](https://mlsanity.com/paper/2311.08441/) (2023)
- [A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA](https://mlsanity.com/paper/2504.03711/) (2025)
- [Message Passing Meets Graph Neural Networks: A New Paradigm for Massive MIMO Systems](https://mlsanity.com/paper/2302.06896/) (2023)
- [Can Graph Neural Networks Help Logic Reasoning?](https://mlsanity.com/paper/1906.02111/) (2019)
- [PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modeling](https://mlsanity.com/paper/2403.00012/) (2024)
- [Revisiting the Message Passing in Heterophilous Graph Neural Networks](https://mlsanity.com/paper/2405.17768/) (2024)
- [Asynchronous Neural Networks for Learning in Graphs](https://mlsanity.com/paper/2205.12245/) (2022)
- [Large Processor Chip Model](https://mlsanity.com/paper/2506.02929/) (2025)
- [Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs](https://mlsanity.com/paper/2507.06549/) (2025)

## Abstract (arXiv)

In traditional EDA flows, layout-level performance metrics are only obtainable after placement and routing, hindering global optimization at earlier stages. Although some neural-network-based solutions predict layout-level performance directly from netlists, they often face generalization challenges due to the black-box heuristics of commercial placement-and-routing tools, which create disparate data across designs. To this end, we propose ParaGate, a three-step cross-stage prediction framework that infers layout-level timing and power from netlists. First, we propose a two-phase transfer-learning approach to predict parasitic parameters, pre-training on mid-scale circuits and fine-tuning on larger ones to capture extreme conditions. Next, we rely on EDA tools for timing analysis, offloading the long-path numerical reasoning. Finally, ParaGate performs global calibration using subgraph features. Experiments show that ParaGate achieves strong generalization with minimal fine-tuning data: on openE906, its arrival-time R2 from 0.119 to 0.897. These results demonstrate that ParaGate could provide guidance for global optimization in the synthesis and placement stages.