# CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference

arXiv: https://arxiv.org/abs/2511.16395 · HTML: https://mlsanity.com/paper/2511.16395/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- Builds on 26 of its 52 references that are in the map.
- First posted on arXiv 20 Nov 2025.

## Builds on (most cited first, 26 of 26)

- [VerilogEval: Evaluating Large Language Models for Verilog Code Generation](https://mlsanity.com/paper/2309.07544/) (2023)
- [VeriGen: A Large Language Model for Verilog Code Generation](https://mlsanity.com/paper/2308.00708/) (2023)
- [Chip-Chat: Challenges and Opportunities in Conversational Hardware Design](https://mlsanity.com/paper/2305.13243/) (2023)
- [Benchmarking Large Language Models for Automated Verilog RTL Code Generation](https://mlsanity.com/paper/2212.11140/) (2022)
- [AutoChip: Automating HDL Generation Using LLM Feedback](https://mlsanity.com/paper/2311.04887/) (2023)
- [GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models](https://mlsanity.com/paper/2309.10730/) (2023)
- [Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS](https://mlsanity.com/paper/2402.03289/) (2024)
- [AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design](https://mlsanity.com/paper/2407.03891/) (2024)
- [AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs](https://mlsanity.com/paper/2402.00386/) (2024)
- [AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators](https://mlsanity.com/paper/2009.14381/) (2020)
- [HLSPilot: LLM-based High-Level Synthesis](https://mlsanity.com/paper/2408.06810/) (2024)
- [Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design](https://mlsanity.com/paper/2407.18276/) (2024)
- [CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design](https://mlsanity.com/paper/2411.08510/) (2024)
- [C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap](https://mlsanity.com/paper/2412.00214/) (2024)
- [C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?](https://mlsanity.com/paper/2406.09233/) (2024)
- [SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design](https://mlsanity.com/paper/2506.02089/) (2025)
- [LLM-Aided Efficient Hardware Design Automation](https://mlsanity.com/paper/2410.18582/) (2024)
- [VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency](https://mlsanity.com/paper/2502.00028/) (2025)
- [HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks](https://mlsanity.com/paper/2504.12268/) (2025)
- [Comparing large language models and human programmers for generating programming code](https://mlsanity.com/paper/2403.00894/) (2024)
- [Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective](https://mlsanity.com/paper/2503.12721/) (2025)
- [Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form](https://mlsanity.com/paper/2506.00005/) (2025)
- [Paradigm-Based Automatic HDL Code Generation Using LLMs](https://mlsanity.com/paper/2501.12702/) (2025)
- [Logic Design of Neural Networks for High-Throughput and Low-Power Applications](https://mlsanity.com/paper/2309.10510/) (2023)
- [VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning](https://mlsanity.com/paper/2511.02285/) (2025)
- [MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design](https://mlsanity.com/paper/2509.13557/) (2025)

## Built on by (most cited first, 3 of 3)

- [Evidence-Driven LLM Agent for C-to-Synthesizable-C Conversion and Verification](https://mlsanity.com/paper/2606.28409/) (2026)
- [LLM for EDA in Front-End Design: Challenges and Opportunities](https://mlsanity.com/paper/2607.09616/) (2026)
- [BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verification](https://mlsanity.com/paper/2609.34785/) (2026)

## Abstract (arXiv)

Large Language Models (LLMs) have demonstrated remarkable potential in hardware front-end design using hardware description languages (HDLs). However, their inherent tendency toward hallucination often introduces functional errors into the generated HDL designs. To address this issue, we propose the framework CorrectHDL that leverages high-level synthesis (HLS) results as functional references to correct potential errors in LLM-generated HDL designs.The input to the proposed framework is a C/C++ program that specifies the target circuit's functionality. The program is provided to an LLM to directly generate an HDL design, whose syntax errors are repaired using a Retrieval-Augmented Generation (RAG) mechanism. The functional correctness of the LLM-generated circuit is iteratively improved by comparing its simulated behavior with an HLS reference design produced by conventional HLS tools, which ensures the functional correctness of the result but can lead to suboptimal area and power efficiency. Experimental results demonstrate that circuits generated by the proposed framework achieve significantly better area and power efficiency than conventional HLS designs and approach the quality of human-engineered circuits. Meanwhile, the correctness of the resulting HDL implementation is maintained, highlighting the effectiveness and potential of agentic HDL design leveraging the generative capabilities of LLMs and the rigor of traditional correctness-driven IC design flows.