# Fast and Compact Tsetlin Machine Inference on CPUs Using Instruction-Level Optimization

arXiv: https://arxiv.org/abs/2510.15653 · HTML: https://mlsanity.com/paper/2510.15653/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Placed in Serving systems and request scheduling, one of 12 directions in Efficient LLM inference and serving.
- Builds on 5 of its 12 references that are in the map.
- First posted on arXiv 17 Oct 2025.

## Placed in

- Efficient LLM inference and serving / [Serving systems and request scheduling](https://mlsanity.com/inference/serving-systems-and-request-scheduling/)

## Builds on (most cited first, 5 of 5)

- [Convergence of Edge Computing and Deep Learning: A Comprehensive Survey](https://mlsanity.com/paper/1907.08349/) (2019)
- [The Tsetlin Machine -- A Game Theoretic Bandit Driven Approach to Optimal Pattern Recognition with Propositional Logic](https://mlsanity.com/paper/1804.01508/) (2018)
- [ETHEREAL: Energy-efficient and High-throughput Inference using Compressed Tsetlin Machine](https://mlsanity.com/paper/2502.05640/) (2025)
- [The bitwise operations related to a fast sorting algorithm](https://mlsanity.com/paper/1312.0138/) (2013)
- [Runtime Tunable Tsetlin Machines for Edge Inference on eFPGAs](https://mlsanity.com/paper/2502.07823/) (2025)

## Built on by (most cited first, 1 of 1)

- [Low-Energy Reduced RISC-V Instruction Subset Processor for Tsetlin Machine Inference at the Edge](https://mlsanity.com/paper/2606.19964/) (2026)

## Abstract (arXiv)

The Tsetlin Machine (TM) offers high-speed inference on resource-constrained devices such as CPUs. Its logic-driven operations naturally lend themselves to parallel execution on modern CPU architectures. Motivated by this, we propose an efficient software implementation of the TM by leveraging instruction-level bitwise operations for compact model representation and accelerated processing. To further improve inference speed, we introduce an early exit mechanism, which exploits the TM's AND-based clause evaluation to avoid unnecessary computations. Building upon this, we propose a literal Reorder strategy designed to maximize the likelihood of early exits. This strategy is applied during a post-training, pre-inference stage through statistical analysis of all literals and the corresponding actions of their associated Tsetlin Automata (TA), introducing negligible runtime overhead. Experimental results using the gem5 simulator with an ARM processor show that our optimized implementation reduces inference time by up to 96.71% compared to the conventional integer-based TM implementations while maintaining comparable code density.