# IntrinTrans: LLM-based Intrinsic Code Translator for RISC-V Vector

arXiv: https://arxiv.org/abs/2510.10119 · HTML: https://mlsanity.com/paper/2510.10119/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 11 Oct 2025.

## Built on by (most cited first, 2 of 2)

- [Instruction Set Migration at Warehouse Scale](https://mlsanity.com/paper/2510.14928/) (2025)
- [AutoVecCoder: Teaching LLMs to Generate Explicitly Vectorized Code](https://mlsanity.com/paper/2605.17978/) (2026)

## Abstract (arXiv)

The use of intrinsic functions to leverage hardware-specific capabilities is a crucial approach for optimizing library performance. Many mainstream libraries implement a large number of vectorized algorithms on Arm or x86 SIMD (Single-Instruction, Multiple-Data) intrinsic functions. Translating existing vectorized intrinsic code into the intrinsics of an emerging architecture is a practical and effective approach. However, current cross-architecture translation largely relies on manual rewriting or rule-based mapping methods, which are both time-consuming and prone to errors. We present textttIntrinTrans, a LLM-based agent that utilizes compile-and-test feedback to translate intrinsic code across architectures automatically, and further optimizes the generated intrinsics using register-usage information derived from liveness analysis. To evaluate the effectiveness of our method, we used textttIntrinTrans to translate the open-source benchmark from Arm Neon Intrinsic to the emerging RISC-V Vector (RVV) Intrinsic implementation and compared its performance with that of the native RVV implementation. Our experiments show that advanced LLMs can generate semantically correct RVV Intrinsic functions with only a finite number of iterations. Depending on the base LLMs, the pass rate ranges from 47% to 100%, achieving performance similar to the native implementation (0.85x to 1.28x).