# NeuroScalar: A Deep Learning Framework for Fast, Accurate, and In-the-Wild Cycle-Level Performance Prediction

arXiv: https://arxiv.org/abs/2509.22410 · HTML: https://mlsanity.com/paper/2509.22410/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 2 of its 30 references that are in the map.
- First posted on arXiv 26 Sep 2025.

## Builds on (most cited first, 2 of 2)

- [Tao: Re-Thinking DL-based Microarchitecture Simulation](https://mlsanity.com/paper/2404.10921/) (2024)
- [Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML Fusion](https://mlsanity.com/paper/2503.23076/) (2025)

## Built on by (most cited first, 1 of 1)

- [On the Limits of Machine-Learned Ranking for Modern Microarchitectural Policies](https://mlsanity.com/paper/2608.01041/) (2026)

## Abstract (arXiv)

The evaluation of new microprocessor designs is constrained by slow, cycle-accurate simulators that rely on unrepresentative benchmark traces. This paper introduces a novel deep learning framework for high-fidelity, ``in-the-wild'' simulation on production hardware. Our core contribution is a DL model trained on microarchitecture-independent features to predict cycle-level performance for hypothetical processor designs. This unique approach allows the model to be deployed on existing silicon to evaluate future hardware. We propose a complete system featuring a lightweight hardware trace collector and a principled sampling strategy to minimize user impact. This system achieves a simulation speed of 5 MIPS on a commodity GPU, imposing a mere 0.1% performance overhead. Furthermore, our co-designed Neutrino on-chip accelerator improves performance by 85x over the GPU. We demonstrate that this framework enables accurate performance analysis and large-scale hardware A/B testing on a massive scale using real-world applications.