# Hybrid unary-binary design for multiplier-less printed Machine Learning classifiers

arXiv: https://arxiv.org/abs/2509.15316 · HTML: https://mlsanity.com/paper/2509.15316/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 5 of its 12 references that are in the map.
- First posted on arXiv 18 Sep 2025.

## Builds on (most cited first, 5 of 5)

- [Cross-Layer Approximation For Printed Machine Learning Circuits](https://mlsanity.com/paper/2203.05915/) (2022)
- [Co-Design of Approximate Multilayer Perceptron for Ultra-Resource Constrained Printed Circuits](https://mlsanity.com/paper/2302.14576/) (2023)
- [Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers](https://mlsanity.com/paper/2303.08255/) (2023)
- [On-sensor Printed Machine Learning Classification via Bespoke ADC and Decision Tree Co-Design](https://mlsanity.com/paper/2312.01172/) (2023)
- [A Bespoke Design Approach to Low-Power Printed Microprocessors for Machine Learning Applications](https://mlsanity.com/paper/2503.21671/) (2025)

## Abstract (arXiv)

Printed Electronics (PE) provide a flexible, cost-efficient alternative to silicon for implementing machine learning (ML) circuits, but their large feature sizes limit classifier complexity. Leveraging PE's low fabrication and NRE costs, designers can tailor hardware to specific ML models, simplifying circuit design. This work explores alternative arithmetic and proposes a hybrid unary-binary architecture that removes costly encoders and enables efficient, multiplier-less execution of MLP classifiers. We also introduce architecture-aware training to further improve area and power efficiency. Evaluation on six datasets shows average reductions of 46% in area and 39% in power, with minimal accuracy loss, surpassing other state-of-the-art MLP designs.