# Application of Machine Learning for Correcting Defect-induced Neuromorphic Circuit Inference Errors

arXiv: https://arxiv.org/abs/2509.11113 · HTML: https://mlsanity.com/paper/2509.11113/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 2 of its 30 references that are in the map.
- First posted on arXiv 14 Sep 2025.

## Builds on (most cited first, 2 of 2)

- [Stuck-at Faults in ReRAM Neuromorphic Circuit Array and their Correction through Machine Learning](https://mlsanity.com/paper/2402.10981/) (2024)
- [Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory](https://mlsanity.com/paper/2105.04212/) (2021)

## Built on by (most cited first, 1 of 1)

- [AI and TCAD for Inverse Design and Defect Discovery: From Simple Machine Learning to LLM](https://mlsanity.com/paper/2609.07046/) (2026)

## Abstract (arXiv)

This paper presents a machine learning-based approach to correct inference errors caused by stuck-at faults in fully analog ReRAM-based neuromorphic circuits. Using a Design-Technology Co-Optimization (DTCO) simulation framework, we model and analyze six spatial defect types-circular, circular-complement, ring, row, column, and checkerboard-across multiple layers of a multi-array neuromorphic architecture. We demonstrate that the proposed correction method, which employs a lightweight neural network trained on the circuit's output voltages, can recover up to 35% (from 55% to 90%) inference accuracy loss in defective scenarios. Our results, based on handwritten digit recognition tasks, show that even small corrective networks can significantly improve circuit robustness. This method offers a scalable and energy-efficient path toward enhanced yield and reliability for neuromorphic systems in edge and internet-of-things (IoTs) applications. In addition to correcting the specific defect types used during training, our method also demonstrates the ability to generalize-achieving reasonable accuracy when tested on different types of defects not seen during training. The framework can be readily extended to support real-time adaptive learning, enabling on-chip correction for dynamic or aging-induced fault profiles.