# Scalable FPGA Framework for Real-Time Denoising in High-Throughput Imaging: A DRAM-Optimized Pipeline using High-Level Synthesis

arXiv: https://arxiv.org/abs/2508.14917 · HTML: https://mlsanity.com/paper/2508.14917/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 1 of its 23 references that are in the map.
- First posted on arXiv 15 Aug 2025.

## Builds on (most cited first, 1 of 1)

- [Low latency optical-based mode tracking with machine learning deployed on FPGAs on a tokamak](https://mlsanity.com/paper/2312.00128/) (2023)

## Abstract (arXiv)

High-throughput imaging workflows, such as Parallel Rapid Imaging with Spectroscopic Mapping (PRISM), generate data at rates that exceed conventional real-time processing capabilities. We present a scalable FPGA-based preprocessing pipeline for real-time denoising, implemented via High-Level Synthesis (HLS) and optimized for DRAM-backed buffering. Our architecture performs frame subtraction and averaging directly on streamed image data, minimizing latency through burst-mode AXI4 interfaces. The resulting kernel operates below the inter-frame interval, enabling inline denoising and reducing dataset size for downstream CPU/GPU analysis. Validated under PRISM-scale acquisition, this modular FPGA framework offers a practical solution for latency-sensitive imaging workflows in spectroscopy and microscopy.