# Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE

arXiv: https://arxiv.org/abs/2508.14899 · HTML: https://mlsanity.com/paper/2508.14899/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 1 of its 6 references that are in the map.
- First posted on arXiv 7 Jul 2025.

## Builds on (most cited first, 1 of 1)

- [MLIR: A Compiler Infrastructure for the End of Moore's Law](https://mlsanity.com/paper/2002.11054/) (2020)

## Abstract (arXiv)

This project enables RISC-V microkernel support in IREE, an MLIR-based machine learning compiler and runtime. The approach begins by enabling the lowering of MLIR linalg dialect contraction ops to linalg.mmt4d op for the RISC-V64 target within the IREE pass pipeline, followed by the development of optimized microkernels for RISC-V. The performance gains are compared with upstream IREE and Llama.cpp for the Llama-3.2-1B-Instruct model.