# OISMA: On-the-fly In-memory Stochastic Multiplication Architecture for Matrix-Multiplication Workloads

arXiv: https://arxiv.org/abs/2508.08822 · HTML: https://mlsanity.com/paper/2508.08822/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- Builds on 6 of its 39 references that are in the map.
- First posted on arXiv 12 Aug 2025.

## Builds on (most cited first, 6 of 6)

- [FP8 Formats for Deep Learning](https://mlsanity.com/paper/2209.05433/) (2022)
- [Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks](https://mlsanity.com/paper/1805.03718/) (2018)
- [DeepScaleTool : A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era](https://mlsanity.com/paper/2102.10195/) (2021)
- [Low-cost Stochastic Number Generators for Stochastic Computing](https://mlsanity.com/paper/2001.02077/) (2020)
- [DiP: A Scalable, Energy-Efficient Systolic Array for Matrix Multiplication Acceleration](https://mlsanity.com/paper/2412.09709/) (2024)
- [A Parallel Bitstream Generator for Stochastic Computing](https://mlsanity.com/paper/1904.09554/) (2019)

## Built on by (most cited first, 2 of 2)

- [DISCA: A Digital In-memory Stochastic Computing Architecture Using A Compressed Bent-Pyramid Format](https://mlsanity.com/paper/2511.17265/) (2025)
- [BenDi: An Energy-Efficient Quasi-Stochastic Systolic Architecture for Edge Bioelectronics](https://mlsanity.com/paper/2606.12235/) (2026)

## Abstract (arXiv)

Artificial intelligence (AI) models are currently driven by a significant upscaling of their complexity, with massive matrix-multiplication workloads representing the major computational bottleneck. In-memory computing (IMC) architectures are proposed to avoid the von Neumann bottleneck. However, both digital/binary-based and analog IMC architectures suffer from various limitations, which significantly degrade the performance and energy efficiency gains. This work proposes OISMA, an energy-efficient IMC architecture that utilizes the computational simplicity of a quasi-stochastic computing (SC) domain (bent-pyramid (BP) system) while keeping the same efficiency, scalability, and productivity of digital memories. OISMA converts normal memory read operations into in situ stochastic multiplication operations with a negligible cost. An accumulation periphery then accumulates the output multiplication bitstreams, achieving the matrix multiplication (MatMul) functionality. A 4-kB 1T1R OISMA array was implemented using a commercial 180-nm technology node and in-house resistive random-access memory (RRAM) technology. At 50 MHz, it achieves 0.789 TOPS/W and 3.98 GOPS/mm2 for energy and area efficiency, respectively, occupying an effective computing area of 0.804241 mm2. Scaling OISMA to 22-nm technology shows a significant improvement of two orders of magnitude in energy efficiency and one order of magnitude in area efficiency, compared to dense MatMul IMC architectures.