# SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation

arXiv: https://arxiv.org/abs/2508.03558 · HTML: https://mlsanity.com/paper/2508.03558/

## Key facts

- Cited by 9 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 5 Aug 2025.

## Built on by (most cited first, 9 of 9)

- [Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation](https://mlsanity.com/paper/2601.19941/) (2026)
- [HLS-Seek: QoR-Aware Code Generation for High-Level Synthesis via Proxy Comparative Reward Reinforcement Learning](https://mlsanity.com/paper/2605.13536/) (2026)
- [Evidence-Driven LLM Agent for C-to-Synthesizable-C Conversion and Verification](https://mlsanity.com/paper/2606.28409/) (2026)
- [From Pragmas to Partners: A Symbiotic Evolution of Agentic High-Level Synthesis](https://mlsanity.com/paper/2602.01401/) (2026)
- [ATLAS: AI-Assisted Threat-to-Assertion Learning for System-on-Chip Security Verification](https://mlsanity.com/paper/2603.01170/) (2026)
- [A3D: Agentic AI flow for autonomous Accelerator Design](https://mlsanity.com/paper/2605.15237/) (2026)
- [CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs](https://mlsanity.com/paper/2606.05680/) (2026)
- [Agentic Electronic Design Automation: A Handoff Perspective](https://mlsanity.com/paper/2606.19795/) (2026)
- [ContractHIL-HLS: Contract-Aligned Multi-Agent Workflow with Hardware-in-the-Loop Feedback for HLS Design](https://mlsanity.com/paper/2607.25283/) (2026)

## Abstract (arXiv)

In today's rapidly evolving field of electronic design automation (EDA), the complexity of hardware designs is increasing, necessitating more sophisticated automation solutions. High-level synthesis (HLS), as a pivotal solution, automates hardware designs from high-level abstractions (e.g., C/C++). However, it faces significant challenges, particularly in design space exploration and optimization. While large language models (LLMs) have shown notable capabilities in code generation, their application to HLS has been limited due to the scarcity of (publicly) available HLS code datasets. Hence, research in this domain has primarily focused on techniques such as prompt engineering and retrieval-augmented generation (RAG). To overcome this limitation, this paper introduces SAGE-HLS, the first-of-its-kind fine-tuned LLM specifically for HLS code generation. Our method includes three key advancements: (i) We implement Verilog-to-C/C++ porting, converting verified and synthesizable Verilog codes into corresponding C, creating a dataset of 16.7K HLS codes; (ii) We implement a fine-tuning strategy, which is based on instruction prompting to code generation guided by abstract syntax tree (AST); (iii) We develop a semi-automated evaluation framework using VerilogEval to assess the functionality of the generated HLS code. Our experiments show that SAGE-HLS, fined-tuned on the QwenCoder (2.5) 7B model, achieves a near 100% success rate in code synthesizability and a 75% success rate in functional correctness.