# Voltage Mode Winner-Take-All Circuit for Neuromorphic Systems

arXiv: https://arxiv.org/abs/2507.04338 · HTML: https://mlsanity.com/paper/2507.04338/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 2 of its 24 references that are in the map.
- First posted on arXiv 6 Jul 2025.

## Builds on (most cited first, 2 of 2)

- [Densely Connected Convolutional Networks](https://mlsanity.com/paper/1608.06993/) (2016)
- [Neuromorphic Architecture for the Hierarchical Temporal Memory](https://mlsanity.com/paper/1808.05839/) (2018)

## Built on by (most cited first, 1 of 1)

- [M2RU: Memristive Minion Recurrent Unit for On-Chip Continual Learning at the Edge](https://mlsanity.com/paper/2512.17299/) (2025)

## Abstract (arXiv)

Recent advances in neuromorphic computing demonstrate on-device learning capabilities with low power consumption. One of the key learning units in these systems is the winner-take-all circuit. In this research, we propose a winner-take-all circuit that can be configured to achieve k-winner and hysteresis properties, simulated in IBM 65 nm node. The circuit dissipated 34.9 μW of power with a latency of 10.4 ns, while processing 1000 inputs. The utility of the circuit is demonstrated for spatial filtering and classification.