# SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models

arXiv: https://arxiv.org/abs/2506.20415 · HTML: https://mlsanity.com/paper/2506.20415/

## Key facts

- Cited by 6 papers in the map (data through 14 Oct 2026).
- Placed in Agent threats, guardrails and governance, one of 16 directions in LLM agents and tool use.
- Builds on 28 of its 81 references that are in the map.
- First posted on arXiv 25 Jun 2025.

## Placed in

- LLM agents and tool use / [Agent threats, guardrails and governance](https://mlsanity.com/agents/agent-threats-guardrails-and-governance/)

## Builds on (most cited first, 28 of 28)

- [AutoDefense: Multi-Agent LLM Defense against Jailbreak Attacks](https://mlsanity.com/paper/2403.04783/) (2024)
- [FinCon: A Synthesized LLM Multi-Agent System with Conceptual Verbal Reinforcement for Enhanced Financial Decision Making](https://mlsanity.com/paper/2407.06567/) (2024)
- [RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models](https://mlsanity.com/paper/2311.16543/) (2023)
- [MACM: Utilizing a Multi-Agent System for Condition Mining in Solving Complex Mathematical Problems](https://mlsanity.com/paper/2404.04735/) (2024)
- [Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction](https://mlsanity.com/paper/2406.00115/) (2024)
- [(Security) Assertions by Large Language Models](https://mlsanity.com/paper/2306.14027/) (2023)
- [HDLdebugger: Streamlining HDL debugging with Large Language Models](https://mlsanity.com/paper/2403.11671/) (2024)
- [Fixing Hardware Security Bugs with Large Language Models](https://mlsanity.com/paper/2302.01215/) (2023)
- [LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation](https://mlsanity.com/paper/2310.04535/) (2023)
- [LLM for SoC Security: A Paradigm Shift](https://mlsanity.com/paper/2310.06046/) (2023)
- [LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debugging](https://mlsanity.com/paper/2401.16448/) (2024)
- [UVLLM: An Automated Universal RTL Verification Framework using LLMs](https://mlsanity.com/paper/2411.16238/) (2024)
- [AssertionBench: A Benchmark to Evaluate Large-Language Models for Assertion Generation](https://mlsanity.com/paper/2406.18627/) (2024)
- [AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL](https://mlsanity.com/paper/2503.19174/) (2025)
- [DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection](https://mlsanity.com/paper/2308.06932/) (2023)
- [VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction](https://mlsanity.com/paper/2504.19099/) (2025)
- [Self-HWDebug: Automation of LLM Self-Instructing for Hardware Security Verification](https://mlsanity.com/paper/2405.12347/) (2024)
- [FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware](https://mlsanity.com/paper/2410.23299/) (2024)
- [Fuzzing Hardware Like Software](https://mlsanity.com/paper/2102.02308/) (2021)
- [Hardware Trojan Detection through Information Flow Security Verification](https://mlsanity.com/paper/1803.04102/) (2018)
- [TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities](https://mlsanity.com/paper/2201.09941/) (2022)
- [BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detection](https://mlsanity.com/paper/2505.22878/) (2025)
- [MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors](https://mlsanity.com/paper/2311.14594/) (2023)
- [HyPFuzz: Formal-Assisted Processor Fuzzing](https://mlsanity.com/paper/2304.02485/) (2023)
- [Automated Hardware Logic Obfuscation Framework Using GPT](https://mlsanity.com/paper/2405.12197/) (2024)
- [FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols](https://mlsanity.com/paper/2504.17226/) (2025)
- [TrojanWhisper: Evaluating Pre-trained LLMs to Detect and Localize Hardware Trojans](https://mlsanity.com/paper/2412.07636/) (2024)
- [Toward Automated Potential Primary Asset Identification in Verilog Designs](https://mlsanity.com/paper/2502.04648/) (2025)

## Built on by (most cited first, 6 of 6)

- [FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures](https://mlsanity.com/paper/2510.15906/) (2025)
- [LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification](https://mlsanity.com/paper/2601.02624/) (2026)
- [Evaluating LLM-Generated ACSL Annotations for Formal Verification](https://mlsanity.com/paper/2602.13851/) (2026)
- [VeriChat: An Agentic Conversational AI Assistant for Hardware Security Verification](https://mlsanity.com/paper/2607.01668/) (2026)
- [An Agentic Framework Using Rules and LLMs for Embedding and Annotating Descriptive Document Layouts: A Plant Science Use Case](https://mlsanity.com/paper/2608.14587/) (2026)
- [A Survey on LLM-Integrated Hardware Design Verification](https://mlsanity.com/paper/2610.10580/) (2026)

## Abstract (arXiv)

Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenges in automation, scalability, comprehensiveness, and adaptability. The advent of large language models (LLMs), with their remarkable capabilities in natural language understanding, code generation, and advanced reasoning, presents a new paradigm for tackling these issues. Moving beyond monolithic models, an agentic approach allows for the creation of multi-agent systems where specialized LLMs collaborate to solve complex problems more effectively. Recognizing this opportunity, we introduce SV-LLM, a novel multi-agent assistant system designed to automate and enhance SoC security verification. By integrating specialized agents for tasks like verification question answering, security asset identification, threat modeling, test plan and property generation, vulnerability detection, and simulation-based bug validation, SV-LLM streamlines the workflow. To optimize their performance in these diverse tasks, agents leverage different learning paradigms, such as in-context learning, fine-tuning, and retrieval-augmented generation (RAG). The system aims to reduce manual intervention, improve accuracy, and accelerate security analysis, supporting proactive identification and mitigation of risks early in the design cycle. We demonstrate its potential to transform hardware security practices through illustrative case studies and experiments that showcase its applicability and efficacy.