# FeNN: A RISC-V vector processor for Spiking Neural Network acceleration

arXiv: https://arxiv.org/abs/2506.11760 · HTML: https://mlsanity.com/paper/2506.11760/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- Builds on 10 of its 26 references that are in the map.
- First posted on arXiv 13 Jun 2025.

## Builds on (most cited first, 10 of 10)

- [Long short-term memory and learning-to-learn in networks of spiking neurons](https://mlsanity.com/paper/1803.09574/) (2018)
- [The Heidelberg spiking datasets for the systematic evaluation of spiking neural networks](https://mlsanity.com/paper/1910.07407/) (2019)
- [Event-Based Backpropagation can compute Exact Gradients for Spiking Neural Networks](https://mlsanity.com/paper/2009.08378/) (2020)
- [A Long Short-Term Memory for AI Applications in Spike-based Neuromorphic Hardware](https://mlsanity.com/paper/2107.03992/) (2021)
- [Efficient Video and Audio processing with Loihi 2](https://mlsanity.com/paper/2310.03251/) (2023)
- [SpiNNaker2: A Large-Scale Neuromorphic System for Event-Based and Asynchronous Machine Learning](https://mlsanity.com/paper/2401.04491/) (2024)
- [Scrambled Linear Pseudorandom Number Generators](https://mlsanity.com/paper/1805.01407/) (2018)
- [Stochastic rounding and reduced-precision fixed-point arithmetic for solving neural ordinary differential equations](https://mlsanity.com/paper/1904.11263/) (2019)
- [Stochastic Rounding: Algorithms and Hardware Accelerator](https://mlsanity.com/paper/2001.01501/) (2020)
- [Even Faster SNN Simulation with Lazy+Event-driven Plasticity and Shared Atomics](https://mlsanity.com/paper/2107.04092/) (2021)

## Built on by (most cited first, 2 of 2)

- [FeNN-DMA: A RISC-V SoC for SNN acceleration](https://mlsanity.com/paper/2511.00732/) (2025)
- [A Symbolic Neural CPU for Quantization-Simulated Writeback and Interpretable Program Execution](https://mlsanity.com/paper/2607.10021/) (2026)

## Abstract (arXiv)

Spiking Neural Networks (SNNs) have the potential to drastically reduce the energy requirements of AI systems. However, mainstream accelerators like GPUs and TPUs are designed for the high arithmetic intensity of standard ANNs so are not well-suited to SNN simulation. FPGAs are well-suited to applications with low arithmetic intensity as they have high off-chip memory bandwidth and large amounts of on-chip memory. Here, we present a novel RISC-V-based soft vector processor (FeNN), tailored to simulating SNNs on FPGAs. Unlike most dedicated neuromorphic hardware, FeNN is fully programmable and designed to be integrated with applications running on standard computers from the edge to the cloud. We demonstrate that, by using stochastic rounding and saturation, FeNN can achieve high numerical precision with low hardware utilisation and that a single FeNN core can simulate an SNN classifier faster than both an embedded GPU and the Loihi neuromorphic system.