# DPUV4E: High-Throughput DPU Architecture Design for CNN on Versal ACAP

arXiv: https://arxiv.org/abs/2506.11441 · HTML: https://mlsanity.com/paper/2506.11441/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- Builds on 15 of its 31 references that are in the map.
- First posted on arXiv 13 Jun 2025.

## Builds on (most cited first, 15 of 15)

- [Deep Residual Learning for Image Recognition](https://mlsanity.com/paper/1512.03385/) (2015)
- [An Image is Worth 16x16 Words: Transformers for Image Recognition at Scale](https://mlsanity.com/paper/2010.11929/) (2020)
- [EfficientNet: Rethinking Model Scaling for Convolutional Neural Networks](https://mlsanity.com/paper/1905.11946/) (2019)
- [MobileNetV2: Inverted Residuals and Linear Bottlenecks](https://mlsanity.com/paper/1801.04381/) (2018)
- [MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications](https://mlsanity.com/paper/1704.04861/) (2017)
- [YOLOv3: An Incremental Improvement](https://mlsanity.com/paper/1804.02767/) (2018)
- [Xception: Deep Learning with Depthwise Separable Convolutions](https://mlsanity.com/paper/1610.02357/) (2016)
- [SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <0.5MB model size](https://mlsanity.com/paper/1602.07360/) (2016)
- [MLPerf Inference Benchmark](https://mlsanity.com/paper/1911.02549/) (2019)
- [DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator](https://mlsanity.com/paper/2008.12745/) (2020)
- [High Performance Depthwise and Pointwise Convolutions on Mobile Devices](https://mlsanity.com/paper/2001.02504/) (2020)
- [MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine](https://mlsanity.com/paper/2311.04980/) (2023)
- [CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture](https://mlsanity.com/paper/2301.02359/) (2023)
- [Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs](https://mlsanity.com/paper/2404.11066/) (2024)
- [H2PIPE: High throughput CNN Inference on FPGAs with High-Bandwidth Memory](https://mlsanity.com/paper/2408.09209/) (2024)

## Built on by (most cited first, 2 of 2)

- [Rethinking Satellite Image Restoration for Onboard AI: A Lightweight Learning-Based Approach](https://mlsanity.com/paper/2604.12807/) (2026)
- [TriCCOT: Tri-part Convolutional Conformal Transformer for Onboard Space Object Detection](https://mlsanity.com/paper/2609.08659/) (2026)

## Abstract (arXiv)

Convolutional Neural Networks (CNNs) remain prevalent in computer vision applications, and FPGAs, known for their flexibility and energy efficiency, have become essential components in heterogeneous acceleration systems. However, traditional FPGAs face challenges in balancing performance and versatility due to limited on-chip resources. AMD's Versal ACAP architecture, tailored for AI applications, incorporates AI Engines (AIEs) to deliver high computational power. Nevertheless, the platform suffers from insufficient memory bandwidth, hindering the full utilization of the AIEs' theoretical performance. In this paper, we present DPUV4E for the Versal architecture, providing configurations ranging from 2PE (32.6 TOPS) to 8PE (131.0 TOPS). We design two computation units, Conv PE and DWC PE, to support different computational patterns. Each computation unit's data flow efficiently utilizes the data reuse opportunities to mitigate bandwidth bottlenecks. Additionally, we extend the functionality of each PE to utilize AIEs for non-convolutional operations, reducing resource overhead. Experiments on over 50 models show that compared to previous designs, our design provides 8.6× the TOPS/W of traditional FPGA-based DPU designs, while reducing DSP usage by 95.8%, LUT usage by 44.7%, and latency to 68.5% under single-batch conditions. For end-to-end inference, our design improving throughput by up to 2.2× for depth-wise convolution models and up to 1.3× for standard models.