# Emerging ML-AI Techniques for Analog and RF EDA

arXiv: https://arxiv.org/abs/2506.00007 · HTML: https://mlsanity.com/paper/2506.00007/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 11 of its 82 references that are in the map.
- First posted on arXiv 12 May 2025.

## Builds on (most cited first, 11 of 11)

- [GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning](https://mlsanity.com/paper/2005.00406/) (2020)
- [ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Models](https://mlsanity.com/paper/2406.18770/) (2024)
- [AmpAgent: An LLM-based Multi-Agent System for Multi-stage Amplifier Schematic Design from Literature for Process and Performance Porting](https://mlsanity.com/paper/2409.14739/) (2024)
- [DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks](https://mlsanity.com/paper/2110.00211/) (2021)
- [An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble](https://mlsanity.com/paper/2106.15412/) (2021)
- [BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks](https://mlsanity.com/paper/1907.10515/) (2019)
- [A general approach for identifying hierarchical symmetry constraints for analog circuit layout](https://mlsanity.com/paper/2010.00051/) (2020)
- [TAG: Learning Circuit Spatial Embedding From Layouts](https://mlsanity.com/paper/2209.03465/) (2022)
- [RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization with Knowledge-infused Reinforcement Learning](https://mlsanity.com/paper/2407.19150/) (2024)
- [ALIGN: A System for Automating Analog Layout](https://mlsanity.com/paper/2008.10682/) (2020)
- [RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL](https://mlsanity.com/paper/2207.06412/) (2022)

## Built on by (most cited first, 1 of 1)

- [VLM-CAD: VLM-Optimized Collaborative Agent Design Workflow for Analog Circuit Sizing](https://mlsanity.com/paper/2601.07315/) (2026)

## Abstract (arXiv)

This survey explores the integration of machine learning (ML) into EDA workflows for analog and RF circuits, addressing challenges unique to analog design, which include complex constraints, nonlinear design spaces, and high computational costs. State-of-the-art learning and optimization techniques are reviewed for circuit tasks such as constraint formulation, topology generation, device modeling, sizing, placement, and routing. The survey highlights the capability of ML to enhance automation, improve design quality, and reduce time-to-market while meeting the target specifications of an analog or RF circuit. Emerging trends and cross-cutting challenges, including robustness to variations and considerations of interconnect parasitics, are also discussed.