# Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing

arXiv: https://arxiv.org/abs/2505.19096 · HTML: https://mlsanity.com/paper/2505.19096/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 12 of its 37 references that are in the map.
- First posted on arXiv 25 May 2025.

## Builds on (most cited first, 12 of 12)

- [Mixed Precision Training](https://mlsanity.com/paper/1710.03740/) (2017)
- [A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices](https://mlsanity.com/paper/1608.08376/) (2016)
- [A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge](https://mlsanity.com/paper/2309.08186/) (2023)
- [FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing](https://mlsanity.com/paper/2007.01530/) (2020)
- [DPU: DAG Processing Unit for Irregular Graphs with Precision-Scalable Posit Arithmetic in 28nm](https://mlsanity.com/paper/2112.05660/) (2021)
- [Training Deep Neural Networks Using Posit Number System](https://mlsanity.com/paper/1909.03831/) (2019)
- [Fixed-Posit: A Floating-Point Representation for Error-Resilient Applications](https://mlsanity.com/paper/2104.04763/) (2021)
- [PERCIVAL: Open-Source Posit RISC-V Core with Quire Capability](https://mlsanity.com/paper/2111.15286/) (2021)
- [The Accuracy and Efficiency of Posit Arithmetic](https://mlsanity.com/paper/2109.08225/) (2021)
- [PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications](https://mlsanity.com/paper/2302.01876/) (2023)
- [Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing](https://mlsanity.com/paper/2305.06946/) (2023)
- [PPU: Design and Implementation of a Pipelined Full Posit Processing Unit](https://mlsanity.com/paper/2308.03425/) (2023)

## Abstract (arXiv)

While posit format offers superior dynamic range and accuracy for transprecision computing, its adoption in RISC-V processors is hindered by the lack of a unified solution for lightweight, precision-scalable, and IEEE-754 arithmetic compatible hardware implementation. To address these challenges, we enhance RISC-V processors by 1) integrating dedicated posit codecs into the original FPU for lightweight implementation, 2) incorporating multi/mixed-precision support with dynamic exponent size for precision-scalability, and 3) reusing and customizing ISA extensions for IEEE-754 compatible posit operations. Our comprehensive evaluation spans the modified FPU, RISC-V core, and SoC levels. It demonstrates that our implementation achieves 47.9% LUTs and 57.4% FFs reduction compared to state-of-the-art posit-enabled RISC-V processors, while achieving up to 2.54× throughput improvement in various GEMM kernels.