# SpikeX: Exploring Accelerator Architecture and Network-Hardware Co-Optimization for Sparse Spiking Neural Networks

arXiv: https://arxiv.org/abs/2505.12292 · HTML: https://mlsanity.com/paper/2505.12292/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 19 of its 49 references that are in the map.
- First posted on arXiv 18 May 2025.

## Builds on (most cited first, 19 of 19)

- [In-Datacenter Performance Analysis of a Tensor Processing Unit](https://mlsanity.com/paper/1704.04760/) (2017)
- [Converting Static Image Datasets to Spiking Neuromorphic Datasets Using Saccades](https://mlsanity.com/paper/1507.07629/) (2015)
- [SLAYER: Spike Layer Error Reassignment in Time](https://mlsanity.com/paper/1810.08646/) (2018)
- [Deep Learning in Spiking Neural Networks](https://mlsanity.com/paper/1804.08150/) (2018)
- [Temporal Spike Sequence Learning via Backpropagation for Deep Spiking Neural Networks](https://mlsanity.com/paper/2002.10085/) (2020)
- [Spike-Train Level Backpropagation for Training Deep Recurrent Spiking Neural Networks](https://mlsanity.com/paper/1908.06378/) (2019)
- [Hybrid Macro/Micro Level Backpropagation for Training Deep Spiking Neural Networks](https://mlsanity.com/paper/1805.07866/) (2018)
- [SCALE-Sim: Systolic CNN Accelerator Simulator](https://mlsanity.com/paper/1811.02883/) (2018)
- [Convolutional Spiking Neural Networks for Spatio-Temporal Feature Extraction](https://mlsanity.com/paper/2003.12346/) (2020)
- [SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks](https://mlsanity.com/paper/2204.05422/) (2022)
- [A Survey of FPGA-Based Neural Network Accelerator](https://mlsanity.com/paper/1712.08934/) (2017)
- [Workload-Balanced Pruning for Sparse Spiking Neural Networks](https://mlsanity.com/paper/2302.06746/) (2023)
- [MINT: Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks](https://mlsanity.com/paper/2305.09850/) (2023)
- [H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks](https://mlsanity.com/paper/2107.11746/) (2021)
- [Sparse Compressed Spiking Neural Network Accelerator for Object Detection](https://mlsanity.com/paper/2205.00778/) (2022)
- [Are SNNs Truly Energy-efficient? - A Hardware Perspective](https://mlsanity.com/paper/2309.03388/) (2023)
- [Spiking Transformer Hardware Accelerators in 3D Integration](https://mlsanity.com/paper/2411.07397/) (2024)
- [Trimming Down Large Spiking Vision Transformers via Heterogeneous Quantization Search](https://mlsanity.com/paper/2412.05505/) (2024)
- [Towards 3D Acceleration for low-power Mixture-of-Experts and Multi-Head Attention Spiking Transformers](https://mlsanity.com/paper/2412.05540/) (2024)

## Built on by (most cited first, 1 of 1)

- [Matterhorn: Masked Time-to-First-Spike Encoding by Reassigning the Silent State for Sparse and Energy-Efficient Spiking Transformers](https://mlsanity.com/paper/2601.22876/) (2026)

## Abstract (arXiv)

Spiking Neural Networks (SNNs) are promising biologically plausible models of computation which utilize a spiking binary activation function similar to that of biological neurons. SNNs are well positioned to process spatiotemporal data, and are advantageous in ultra-low power and real-time processing. Despite a large body of work on conventional artificial neural network accelerators, much less attention has been given to efficient SNN hardware accelerator design. In particular, SNNs exhibit inherent unstructured spatial and temporal firing sparsity, an opportunity yet to be fully explored for great hardware processing efficiency. In this work, we propose a novel systolic-array SNN accelerator architecture, called SpikeX, to take on the challenges and opportunities stemming from unstructured sparsity while taking into account the unique characteristics of spike-based computation. By developing an efficient dataflow targeting expensive multi-bit weight data movements, SpikeX reduces memory access and increases data sharing and hardware utilization for computations spanning across both time and space, thereby significantly improving energy efficiency and inference latency. Furthermore, recognizing the importance of SNN network and hardware co-design, we develop a co-optimization methodology facilitating not only hardware-aware SNN training but also hardware accelerator architecture search, allowing joint network weight parameter optimization and accelerator architectural reconfiguration. This end-to-end network/accelerator co-design approach offers a significant reduction of 15.1x-150.87x in energy-delay-product(EDP) without comprising model accuracy.