# CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture

arXiv: https://arxiv.org/abs/2505.03762 · HTML: https://mlsanity.com/paper/2505.03762/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 20 Apr 2025.

## Built on by (most cited first, 1 of 1)

- [FeNN-DMA: A RISC-V SoC for SNN acceleration](https://mlsanity.com/paper/2511.00732/) (2025)

## Abstract (arXiv)

Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on the industry-supported open-source CVA6 core and its superscalar variant, CVA6S, we introduce CVA6S+, an enhanced version incorporating improved branch prediction, register renaming and enhanced operand forwarding. These optimizations enable CVA6S+ to achieve a 43.5% performance improvement over the scalar configuration and 10.9% over CVA6S, with an area overhead of just 9.30% over the scalar core (CVA6). Furthermore, we integrate CVA6S+ with the OpenHW Core-V High-Performance L1 Dcache (HPDCache) and report a 74.1% bandwidth improvement over the legacy CVA6 cache subsystem.