# CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures

arXiv: https://arxiv.org/abs/2505.01107 · HTML: https://mlsanity.com/paper/2505.01107/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 7 of its 26 references that are in the map.
- First posted on arXiv 2 May 2025.

## Builds on (most cited first, 7 of 7)

- [AI and Memory Wall](https://mlsanity.com/paper/2403.14123/) (2024)
- [PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference](https://mlsanity.com/paper/1901.10351/) (2019)
- [CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators](https://mlsanity.com/paper/2401.12428/) (2024)
- [PIMCOMP: A Universal Compilation Framework for Crossbar-based PIM DNN Accelerators](https://mlsanity.com/paper/2307.01475/) (2023)
- [Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity](https://mlsanity.com/paper/2404.09497/) (2024)
- [NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration](https://mlsanity.com/paper/2204.09989/) (2022)
- [DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory](https://mlsanity.com/paper/2310.20424/) (2023)

## Built on by (most cited first, 1 of 1)

- [SciFlow-Bench: Evaluating Structure-Aware Scientific Diagram Generation via Inverse Parsing](https://mlsanity.com/paper/2602.09809/) (2026)

## Abstract (arXiv)

Digital Compute-in-Memory (CIM) architectures have shown great promise in Deep Neural Network (DNN) acceleration by effectively addressing the "memory wall" bottleneck. However, the development and optimization of digital CIM accelerators are hindered by the lack of comprehensive tools that encompass both software and hardware design spaces. Moreover, existing design and evaluation frameworks often lack support for the capacity constraints inherent in digital CIM architectures. In this paper, we present CIMFlow, an integrated framework that provides an out-of-the-box workflow for implementing and evaluating DNN workloads on digital CIM architectures. CIMFlow bridges the compilation and simulation infrastructures with a flexible instruction set architecture (ISA) design, and addresses the constraints of digital CIM through advanced partitioning and parallelism strategies in the compilation flow. Our evaluation demonstrates that CIMFlow enables systematic prototyping and optimization of digital CIM architectures across diverse configurations, providing researchers and designers with an accessible platform for extensive design space exploration.