# NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph

arXiv: https://arxiv.org/abs/2504.09260 · HTML: https://mlsanity.com/paper/2504.09260/

## Key facts

- Cited by 9 papers in the map (data through 14 Oct 2026).
- Builds on 23 of its 48 references that are in the map.
- First posted on arXiv 12 Apr 2025.

## Builds on (most cited first, 23 of 23)

- [The Llama 3 Herd of Models](https://mlsanity.com/paper/2407.21783/) (2024)
- [Representation Learning with Contrastive Predictive Coding](https://mlsanity.com/paper/1807.03748/) (2018)
- [MTEB: Massive Text Embedding Benchmark](https://mlsanity.com/paper/2210.07316/) (2022)
- [NV-Embed: Improved Techniques for Training LLMs as Generalist Embedding Models](https://mlsanity.com/paper/2405.17428/) (2024)
- [LLM2Vec: Large Language Models Are Secretly Powerful Text Encoders](https://mlsanity.com/paper/2404.05961/) (2024)
- [One for All: Towards Training One Graph Model for All Classification Tasks](https://mlsanity.com/paper/2310.00149/) (2023)
- [Harnessing Explanations: LLM-to-LM Interpreter for Enhanced Text-Attributed Graph Representation Learning](https://mlsanity.com/paper/2305.19523/) (2023)
- [SGFormer: Simplifying and Empowering Transformers for Large-Graph Representations](https://mlsanity.com/paper/2306.10759/) (2023)
- [ChatEDA: A Large Language Model Powered Autonomous Agent for EDA](https://mlsanity.com/paper/2308.10204/) (2023)
- [BetterV: Controlled Verilog Generation with Discriminative Guidance](https://mlsanity.com/paper/2402.03375/) (2024)
- [DeepGate: Learning Neural Representations of Logic Gates](https://mlsanity.com/paper/2111.14616/) (2021)
- [DeepGate2: Functionality-Aware Circuit Representation Learning](https://mlsanity.com/paper/2305.16373/) (2023)
- [AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs](https://mlsanity.com/paper/2402.00386/) (2024)
- [Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks](https://mlsanity.com/paper/2303.08256/) (2023)
- [DeepGate3: Towards Scalable Circuit Representation Learning](https://mlsanity.com/paper/2407.11095/) (2024)
- [MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design](https://mlsanity.com/paper/2311.08441/) (2023)
- [A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA](https://mlsanity.com/paper/2504.03711/) (2025)
- [The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models](https://mlsanity.com/paper/2403.07257/) (2024)
- [TAG: Learning Circuit Spatial Embedding From Layouts](https://mlsanity.com/paper/2209.03465/) (2022)
- [DeepSeq: Deep Sequential Circuit Learning](https://mlsanity.com/paper/2302.13608/) (2023)
- [DE-HNN: An effective neural model for Circuit Netlist representation](https://mlsanity.com/paper/2404.00477/) (2024)
- [Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization](https://mlsanity.com/paper/2403.18453/) (2024)
- [ReIGNN: State Register Identification Using Graph Neural Networks for Circuit Reverse Engineering](https://mlsanity.com/paper/2112.00806/) (2021)

## Built on by (most cited first, 9 of 9)

- [NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestration](https://mlsanity.com/paper/2512.00119/) (2025)
- [Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilities](https://mlsanity.com/paper/2508.04235/) (2025)
- [GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment](https://mlsanity.com/paper/2504.09485/) (2025)
- [AnalogRetriever: Learning Cross-Modal Representations for Analog Circuit Retrieval](https://mlsanity.com/paper/2604.23195/) (2026)
- [Modeling Relational Logic Circuits for And-Inverter Graph Convolutional Network](https://mlsanity.com/paper/2508.11991/) (2025)
- [TRACE: Learning to Compute on Circuit Graphs](https://mlsanity.com/paper/2509.21886/) (2025)
- [Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation](https://mlsanity.com/paper/2605.08291/) (2026)
- [Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits](https://mlsanity.com/paper/2608.28188/) (2026)
- [LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks](https://mlsanity.com/paper/2609.03594/) (2026)

## Abstract (arXiv)

Circuit representation learning has shown promise in advancing Electronic Design Automation (EDA) by capturing structural and functional circuit properties for various tasks. Existing pre-trained solutions rely on graph learning with complex functional supervision, such as truth table simulation. However, they only handle simple and-inverter graphs (AIGs), struggling to fully encode other complex gate functionalities. While large language models (LLMs) excel at functional understanding, they lack the structural awareness for flattened netlists. To advance netlist representation learning, we present NetTAG, a netlist foundation model that fuses gate semantics with graph structure, handling diverse gate types and supporting a variety of functional and physical tasks. Moving beyond existing graph-only methods, NetTAG formulates netlists as text-attributed graphs, with gates annotated by symbolic logic expressions and physical characteristics as text attributes. Its multimodal architecture combines an LLM-based text encoder for gate semantics and a graph transformer for global structure. Pre-trained with gate and graph self-supervised objectives and aligned with RTL and layout stages, NetTAG captures comprehensive circuit intrinsics. Experimental results show that NetTAG consistently outperforms each task-specific method on four largely different functional and physical tasks and surpasses state-of-the-art AIG encoders, demonstrating its versatility.