# Review of Machine Learning for Micro-Electronic Design Verification

arXiv: https://arxiv.org/abs/2503.11687 · HTML: https://mlsanity.com/paper/2503.11687/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 12 of its 111 references that are in the map.
- First posted on arXiv 5 Mar 2025.

## Builds on (most cited first, 12 of 12)

- [OpenAI Gym](https://mlsanity.com/paper/1606.01540/) (2016)
- [Machine Learning for Electronic Design Automation: A Survey](https://mlsanity.com/paper/2102.03357/) (2021)
- [AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design](https://mlsanity.com/paper/2407.03891/) (2024)
- [Using Neural Networks for Novelty-based Test Selection to Accelerate Functional Coverage Closure](https://mlsanity.com/paper/2207.00445/) (2022)
- [Efficient Stimuli Generation using Reinforcement Learning in Design Verification](https://mlsanity.com/paper/2405.19815/) (2024)
- [Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification](https://mlsanity.com/paper/2205.08524/) (2022)
- [Design Rule Checking with a CNN Based Feature Extractor](https://mlsanity.com/paper/2012.11510/) (2020)
- [VeRLPy: Python Library for Verification of Digital Designs with Reinforcement Learning](https://mlsanity.com/paper/2108.03978/) (2021)
- [VeriBug: An Attention-based Framework for Bug-Localization in Hardware Designs](https://mlsanity.com/paper/2401.09494/) (2024)
- [Hybrid Intelligent Testing in Simulation-Based Verification](https://mlsanity.com/paper/2205.09552/) (2022)
- [Detecting Stimuli with Novel Temporal Patterns to Accelerate Functional Coverage Closure](https://mlsanity.com/paper/2407.02510/) (2024)
- [The Integration of Machine Learning into Automated Test Generation: A Systematic Mapping Study](https://mlsanity.com/paper/2206.10210/) (2022)

## Built on by (most cited first, 1 of 1)

- [BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis](https://mlsanity.com/paper/2506.10501/) (2025)

## Abstract (arXiv)

Microelectronic design verification remains a critical bottleneck in device development, traditionally mitigated by expanding verification teams and computational resources. Since the late 1990s, machine learning (ML) has been proposed to enhance verification efficiency, yet many techniques have not achieved mainstream adoption. This review, from the perspective of verification and ML practitioners, examines the application of ML in dynamic-based techniques for functional verification of microelectronic designs, and provides a starting point for those new to this interdisciplinary field. Historical trends, techniques, ML types, and evaluation baselines are analysed to understand why previous research has not been widely adopted in industry. The review highlights the application of ML, the techniques used and critically discusses their limitations and successes. Although there is a wealth of promising research, real-world adoption is hindered by challenges in comparing techniques, identifying suitable applications, and the expertise required for implementation. This review proposes that the field can progress through the creation and use of open datasets, common benchmarks, and verification targets. By establishing open evaluation criteria, industry can guide future research. Parallels with ML in software verification suggest potential for collaboration. Additionally, greater use of open-source designs and verification environments can allow more researchers from outside the hardware verification discipline to contribute to the challenge of verifying microelectronic designs.