# CORDIC Is All You Need

arXiv: https://arxiv.org/abs/2503.11685 · HTML: https://mlsanity.com/paper/2503.11685/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 10 of its 76 references that are in the map.
- First posted on arXiv 4 Mar 2025.

## Builds on (most cited first, 10 of 10)

- [Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding](https://mlsanity.com/paper/1510.00149/) (2015)
- [EIE: Efficient Inference Engine on Compressed Deep Neural Network](https://mlsanity.com/paper/1602.01528/) (2016)
- [NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps](https://mlsanity.com/paper/1706.01406/) (2017)
- [Systolic Tensor Array: An Efficient Structured-Sparse GEMM Accelerator for Mobile CNN Inference](https://mlsanity.com/paper/2005.08098/) (2020)
- [Layer-specific Optimization for Mixed Data Flow with Mixed Precision in FPGA Design for CNN-based Object Detectors](https://mlsanity.com/paper/2009.01588/) (2020)
- [Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In](https://mlsanity.com/paper/2305.04760/) (2023)
- [Low Precision Floating-point Arithmetic for High Performance FPGA-based CNN Acceleration](https://mlsanity.com/paper/2003.03852/) (2020)
- [FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching](https://mlsanity.com/paper/2405.13170/) (2024)
- [Sustainable AI Processing at the Edge](https://mlsanity.com/paper/2207.01209/) (2022)
- [HOAA: Hybrid Overestimating Approximate Adder for Enhanced Performance Processing Engine](https://mlsanity.com/paper/2408.00806/) (2024)

## Abstract (arXiv)

Artificial intelligence necessitates adaptable hardware accelerators for efficient high-throughput million operations. We present pipelined architecture with CORDIC block for linear MAC computations and nonlinear iterative Activation Functions (AF) such as tanh, sigmoid, and softmax. This approach focuses on a Reconfigurable Processing Engine (RPE) based systolic array, with 40% pruning rate, enhanced throughput up to 4.64×, and reduction in power and area by 5.02 × and 4.06 × at CMOS 28 nm, with minor accuracy loss. FPGA implementation achieves a reduction of up to 2.5 × resource savings and 3 × power compared to prior works. The Systolic CORDIC engine for Reconfigurability and Enhanced throughput (SYCore) deploys an output stationary dataflow with the CAESAR control engine for diverse AI workloads such as Transformers, RNNs/LSTMs, and DNNs for applications like image detection, LLMs, and speech recognition. The energy-efficient and flexible approach extends the enhanced approach for edge AI accelerators supporting emerging workloads.