# Timing-Driven Global Placement by Efficient Critical Path Extraction

arXiv: https://arxiv.org/abs/2503.11674 · HTML: https://mlsanity.com/paper/2503.11674/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- Builds on 1 of its 30 references that are in the map.
- First posted on arXiv 28 Feb 2025.

## Builds on (most cited first, 1 of 1)

- [Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms](https://mlsanity.com/paper/2407.15026/) (2024)

## Built on by (most cited first, 4 of 4)

- [BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement](https://mlsanity.com/paper/2510.23472/) (2025)
- [Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation](https://mlsanity.com/paper/2503.12946/) (2025)
- [Beyond the Node: Clade-level Selection for Efficient MCTS in Automatic Heuristic Design](https://mlsanity.com/paper/2602.00549/) (2026)
- [Re2MaP: Macro Placement by Recursively Prototyping and Packing Tree-based Relocating](https://mlsanity.com/paper/2511.08054/) (2025)

## Abstract (arXiv)

Timing optimization during the global placement of integrated circuits has been a significant focus for decades, yet it remains a complex, unresolved issue. Recent analytical methods typically use pin-level timing information to adjust net weights, which is fast and simple but neglects the path-based nature of the timing graph. The existing path-based methods, however, cannot balance the accuracy and efficiency due to the exponential growth of number of critical paths. In this work, we propose a GPU-accelerated timing-driven global placement framework, integrating accurate path-level information into the efficient DREAMPlace infrastructure. It optimizes the fine-grained pin-to-pin attraction objective and is facilitated by efficient critical path extraction. We also design a quadratic distance loss function specifically to align with the RC timing model. Experimental results demonstrate that our method significantly outperforms the current leading timing-driven placers, achieving an average improvement of 40.5% in total negative slack (TNS) and 8.3% in worst negative slack (WNS), as well as an improvement in half-perimeter wirelength (HPWL).