# FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inference

arXiv: https://arxiv.org/abs/2503.04426 · HTML: https://mlsanity.com/paper/2503.04426/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 12 of its 51 references that are in the map.
- First posted on arXiv 6 Mar 2025.

## Builds on (most cited first, 12 of 12)

- [In-Datacenter Performance Analysis of a Tensor Processing Unit](https://mlsanity.com/paper/1704.04760/) (2017)
- [Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration](https://mlsanity.com/paper/1911.09925/) (2019)
- [FT-ClipAct: Resilience Analysis of Deep Neural Networks and Improving their Fault Tolerance using Clipped Activation](https://mlsanity.com/paper/1912.00941/) (2019)
- [A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks](https://mlsanity.com/paper/2305.05750/) (2023)
- [FAT: Training Neural Networks for Reliable Inference Under Hardware Faults](https://mlsanity.com/paper/2011.05873/) (2020)
- [Fast and Accurate Error Simulation for CNNs against Soft Errors](https://mlsanity.com/paper/2206.02051/) (2022)
- [Enhancing Fault Resilience of QNNs by Selective Neuron Splitting](https://mlsanity.com/paper/2306.09973/) (2023)
- [A Low-cost Strategic Monitoring Approach for Scalable and Interpretable Error Detection in Deep Neural Networks](https://mlsanity.com/paper/2310.20349/) (2023)
- [SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators](https://mlsanity.com/paper/2403.02946/) (2024)
- [ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining](https://mlsanity.com/paper/2211.12600/) (2022)
- [Error Checking for Sparse Systolic Tensor Arrays](https://mlsanity.com/paper/2402.10850/) (2024)
- [On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster](https://mlsanity.com/paper/2205.12580/) (2022)

## Built on by (most cited first, 1 of 1)

- [FLARE: One-Shot PE-Level Fault Localization in Systolic Arrays via Algebraic Test Vectors](https://mlsanity.com/paper/2605.08594/) (2026)

## Abstract (arXiv)

The emergence of Deep Neural Networks (DNNs) in mission- and safety-critical applications brings their reliability to the front. High performance demands of DNNs require the use of specialized hardware accelerators. Systolic array architecture is widely used in DNN accelerators due to its parallelism and regular structure. This work presents a run-time reconfigurable systolic array architecture with three execution modes and four implementation options. All four implementations are evaluated in terms of resource utilization, throughput, and fault tolerance improvement. The proposed architecture is used for reliability enhancement of DNN inference on systolic array through heterogeneous mapping of different network layers to different execution modes. The approach is supported by a novel reliability assessment method based on fault propagation analysis. It is used for the exploration of the appropriate execution mode--layer mapping for DNN inference. The proposed architecture efficiently protects registers and MAC units of systolic array PEs from transient and permanent faults. The reconfigurability feature enables a speedup of up to 3×, depending on layer vulnerability. Furthermore, it requires 6× fewer resources compared to static redundancy and 2.5× fewer resources compared to the previously proposed solution for transient faults.