# AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies

arXiv: https://arxiv.org/abs/2503.00205 · HTML: https://mlsanity.com/paper/2503.00205/

## Key facts

- Cited by 37 papers in the map (data through 14 Oct 2026).
- Builds on 18 of its 34 references that are in the map.
- First posted on arXiv 28 Feb 2025.

## Builds on (most cited first, 18 of 18)

- [GPT-4 Technical Report](https://mlsanity.com/paper/2303.08774/) (2023)
- [GraphRNN: Generating Realistic Graphs with Deep Auto-regressive Models](https://mlsanity.com/paper/1802.08773/) (2018)
- [VerilogEval: Evaluating Large Language Models for Verilog Code Generation](https://mlsanity.com/paper/2309.07544/) (2023)
- [VeriGen: A Large Language Model for Verilog Code Generation](https://mlsanity.com/paper/2308.00708/) (2023)
- [ChipNeMo: Domain-Adapted LLMs for Chip Design](https://mlsanity.com/paper/2311.00176/) (2023)
- [Chip-Chat: Challenges and Opportunities in Conversational Hardware Design](https://mlsanity.com/paper/2305.13243/) (2023)
- [ChatEDA: A Large Language Model Powered Autonomous Agent for EDA](https://mlsanity.com/paper/2308.10204/) (2023)
- [ChipGPT: How far are we from natural language hardware design](https://mlsanity.com/paper/2305.14019/) (2023)
- [GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning](https://mlsanity.com/paper/2005.00406/) (2020)
- [AnalogCoder: Analog Circuit Design via Training-Free Code Generation](https://mlsanity.com/paper/2405.14918/) (2024)
- [AutoChip: Automating HDL Generation Using LLM Feedback](https://mlsanity.com/paper/2311.04887/) (2023)
- [A Survey on Deep Graph Generation: Methods and Applications](https://mlsanity.com/paper/2203.06714/) (2022)
- [GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models](https://mlsanity.com/paper/2309.10730/) (2023)
- [CktGNN: Circuit Graph Neural Network for Electronic Design Automation](https://mlsanity.com/paper/2308.16406/) (2023)
- [LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation](https://mlsanity.com/paper/2401.12224/) (2023)
- [LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits](https://mlsanity.com/paper/2407.18269/) (2024)
- [Domain Knowledge-Infused Deep Learning for Automated Analog/Radio-Frequency Circuit Parameter Optimization](https://mlsanity.com/paper/2204.12948/) (2022)
- [RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization with Knowledge-infused Reinforcement Learning](https://mlsanity.com/paper/2407.19150/) (2024)

## Built on by (most cited first, 30 of 37)

- [AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuits](https://mlsanity.com/paper/2505.24138/) (2025)
- [AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs](https://mlsanity.com/paper/2508.02518/) (2025)
- [AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing](https://mlsanity.com/paper/2511.03697/) (2025)
- [AMSnet 2.0: A Large AMS Database with AI Segmentation for Net Detection](https://mlsanity.com/paper/2505.09155/) (2025)
- [HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization](https://mlsanity.com/paper/2511.19669/) (2025)
- [AnalogAgent: Self-Improving Analog Circuit Design Automation with LLM Agents](https://mlsanity.com/paper/2603.23910/) (2026)
- [CircuitSense: A Hierarchical MLLM Benchmark Bridging Visual Comprehension and Symbolic Reasoning in Engineering Design Process](https://mlsanity.com/paper/2509.22339/) (2025)
- [OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation](https://mlsanity.com/paper/2601.19439/) (2026)
- [Graph Tokenization for Bridging Graphs and Transformers](https://mlsanity.com/paper/2603.11099/) (2026)
- [ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddings](https://mlsanity.com/paper/2511.07658/) (2025)
- [CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language Prompt](https://mlsanity.com/paper/2605.05773/) (2026)
- [SPICEMixer - Netlist-Level Circuit Evolution](https://mlsanity.com/paper/2506.01497/) (2025)
- [When Forgetting Builds Reliability: LLM Unlearning for Reliable Hardware Code Generation](https://mlsanity.com/paper/2512.05341/) (2025)
- [PowerGenie: Analytically-Guided Evolutionary Discovery of Superior Reconfigurable Power Converters](https://mlsanity.com/paper/2601.21984/) (2026)
- [AstRL: Analog and Mixed-Signal Circuit Synthesis with Deep Reinforcement Learning](https://mlsanity.com/paper/2602.12402/) (2026)
- [R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII](https://mlsanity.com/paper/2604.08810/) (2026)
- [AnalogRetriever: Learning Cross-Modal Representations for Analog Circuit Retrieval](https://mlsanity.com/paper/2604.23195/) (2026)
- [RF-Agent: A Practical Framework for Building Language Agents for RFIC Design](https://mlsanity.com/paper/2607.18772/) (2026)
- [NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation](https://mlsanity.com/paper/2608.12197/) (2026)
- [PrefixAgent: An LLM-Powered Design Framework for Efficient Prefix Adder Optimization](https://mlsanity.com/paper/2507.06127/) (2025)
- [AnalogFed: Privacy-Preserving Discovery of Analog Circuits at Scale with Federated Generative AI](https://mlsanity.com/paper/2507.15104/) (2025)
- [SchGen: PCB Schematic Generation with Semantic-Grounded Code Representations](https://mlsanity.com/paper/2605.30345/) (2026)
- [SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence](https://mlsanity.com/paper/2607.01609/) (2026)
- [EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models](https://mlsanity.com/paper/2607.13416/) (2026)
- [ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits](https://mlsanity.com/paper/2607.23225/) (2026)
- [Finding the Needle in a Haystack: Test-Time Analog Circuit Representation Adaptation for Bayesian Optimization](https://mlsanity.com/paper/2608.12687/) (2026)
- [AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models](https://mlsanity.com/paper/2608.13472/) (2026)
- [Spicing up Genetic Netlist Generation with LLMs](https://mlsanity.com/paper/2608.23317/) (2026)
- [Analog-DB: An Agent-First Analog Integrated Circuit Database, From Blocks to Systems](https://mlsanity.com/paper/2609.01286/) (2026)
- [Circuit-MLLM: Topological Logic-Guided Latent-Space Visual Reasoning for Circuit Schematic Understanding](https://mlsanity.com/paper/2609.15668/) (2026)

## Abstract (arXiv)

The massive and large-scale design of foundational semiconductor integrated circuits (ICs) is crucial to sustaining the advancement of many emerging and future technologies, such as generative AI, 5G/6G, and quantum computing. Excitingly, recent studies have shown the great capabilities of foundational models in expediting the design of digital ICs. Yet, applying generative AI techniques to accelerate the design of analog ICs remains a significant challenge due to critical domain-specific issues, such as the lack of a comprehensive dataset and effective representation methods for analog circuits. This paper proposes, AnalogGenie, a underlineGeneratunderlineive underlineengine for automatic design/discovery of underlineAnalog circuit topologies--the most challenging and creative task in the conventional manual design flow of analog ICs. AnalogGenie addresses two key gaps in the field: building a foundational comprehensive dataset of analog circuit topology and developing a scalable sequence-based graph representation universal to analog circuits. Experimental results show the remarkable generation performance of AnalogGenie in broadening the variety of analog ICs, increasing the number of devices within a single design, and discovering unseen circuit topologies far beyond any prior arts. Our work paves the way to transform the longstanding time-consuming manual design flow of analog ICs to an automatic and massive manner powered by generative AI. Our source code is available at https://github.com/xz-group/AnalogGenie.