# An All-digital 8.6-nJ/Frame 65-nm Tsetlin Machine Image Classification Accelerator

arXiv: https://arxiv.org/abs/2501.19347 · HTML: https://mlsanity.com/paper/2501.19347/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- Builds on 14 of its 51 references that are in the map.
- First posted on arXiv 31 Jan 2025.

## Builds on (most cited first, 14 of 14)

- [Efficient Processing of Deep Neural Networks: A Tutorial and Survey](https://mlsanity.com/paper/1703.09039/) (2017)
- [MLPerf Tiny Benchmark](https://mlsanity.com/paper/2106.07597/) (2021)
- [The Tsetlin Machine -- A Game Theoretic Bandit Driven Approach to Optimal Pattern Recognition with Propositional Logic](https://mlsanity.com/paper/1804.01508/) (2018)
- [The Convolutional Tsetlin Machine](https://mlsanity.com/paper/1905.09688/) (2019)
- [XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference](https://mlsanity.com/paper/1807.03010/) (2018)
- [Coalesced Multi-Output Tsetlin Machines with Clause Sharing](https://mlsanity.com/paper/2108.07594/) (2021)
- [The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design](https://mlsanity.com/paper/1911.05289/) (2019)
- [Building Concise Logical Patterns by Constraining Tsetlin Machine Clause Size](https://mlsanity.com/paper/2301.08190/) (2023)
- [An Optimized Toolbox for Advanced Image Processing with Tsetlin Machine Composites](https://mlsanity.com/paper/2406.00704/) (2024)
- [Low-Latency Asynchronous Logic Design for Inference at the Edge](https://mlsanity.com/paper/2012.03402/) (2020)
- [TMComposites: Plug-and-Play Collaboration Between Specialized Tsetlin Machines](https://mlsanity.com/paper/2309.04801/) (2023)
- [IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines](https://mlsanity.com/paper/2305.12914/) (2023)
- [Self-timed Reinforcement Learning using Tsetlin Machine](https://mlsanity.com/paper/2109.00846/) (2021)
- [In-Memory Learning Automata Architecture using Y-Flash Cell](https://mlsanity.com/paper/2408.09456/) (2024)

## Built on by (most cited first, 3 of 3)

- [Scalable Bayesian Network Structure Learning Using Tsetlin Machine to Constrain the Search Space](https://mlsanity.com/paper/2511.19273/) (2025)
- [Explainable and Hardware-Efficient Jamming Detection for 5G Networks Using the Convolutional Tsetlin Machine](https://mlsanity.com/paper/2603.07336/) (2026)
- [FastOmniTMAE: Parallel Clause Learning for Scalable and Hardware-Efficient Tsetlin Embeddings](https://mlsanity.com/paper/2605.06982/) (2026)

## Abstract (arXiv)

We present an all-digital programmable machine learning accelerator chip for image classification, underpinning on the Tsetlin machine (TM) principles. The TM is an emerging machine learning algorithm founded on propositional logic, utilizing sub-pattern recognition expressions called clauses. The accelerator implements the coalesced TM version with convolution, and classifies booleanized images of 28×28 pixels with 10 categories. A configuration with 128 clauses is used in a highly parallel architecture. Fast clause evaluation is achieved by keeping all clause weights and Tsetlin automata (TA) action signals in registers. The chip is implemented in a 65 nm low-leakage CMOS technology, and occupies an active area of 2.7 mm2. At a clock frequency of 27.8 MHz, the accelerator achieves 60.3k classifications per second, and consumes 8.6 nJ per classification. This demonstrates the energy-efficiency of the TM, which was the main motivation for developing this chip. The latency for classifying a single image is 25.4 μs which includes system timing overhead. The accelerator achieves 97.42%, 84.54% and 82.55% test accuracies for the datasets MNIST, Fashion-MNIST and Kuzushiji-MNIST, respectively, matching the TM software models.