# Chip-to-chip photonic connectivity in multi-accelerator servers for ML

arXiv: https://arxiv.org/abs/2501.18169 · HTML: https://mlsanity.com/paper/2501.18169/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 30 Jan 2025.

## Built on by (most cited first, 2 of 2)

- [LUMION: Fast Fault Recovery for ML Jobs Using Programmable Optical Fabrics](https://mlsanity.com/paper/2505.23105/) (2025)
- [Morphlux: Transforming Torus Fabrics for Efficient Multi-tenant ML](https://mlsanity.com/paper/2508.03674/) (2025)

## Abstract (arXiv)

We present a rack-scale compute architecture for ML using multi-accelerator servers connected via chip-to-chip silicon photonic components. Our architecture achieves (1) multi-tenanted resource slicing without fragmentation, (2) 74% faster rack-scale collective communication, and (3) 1.7X speedup in end-to-end ML training throughput.