# Exploring the Potential of Wireless-enabled Multi-Chip AI Accelerators

arXiv: https://arxiv.org/abs/2501.17567 · HTML: https://mlsanity.com/paper/2501.17567/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 9 of its 31 references that are in the map.
- First posted on arXiv 29 Jan 2025.

## Builds on (most cited first, 9 of 9)

- [Training Compute-Optimal Large Language Models](https://mlsanity.com/paper/2203.15556/) (2022)
- [A Survey of Transformers](https://mlsanity.com/paper/2106.04554/) (2021)
- [Computing Graph Neural Networks: A Survey from Algorithms to Accelerators](https://mlsanity.com/paper/2010.00130/) (2020)
- [Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators](https://mlsanity.com/paper/2312.16436/) (2023)
- [SCAR: Scheduling Multi-Model AI Workloads on Heterogeneous Multi-Chiplet Module Accelerators](https://mlsanity.com/paper/2405.00790/) (2024)
- [Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-based Accelerators](https://mlsanity.com/paper/2210.14657/) (2022)
- [Communication Characterization of AI Workloads for Large-scale Multi-chiplet Accelerators](https://mlsanity.com/paper/2410.22262/) (2024)
- [Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors](https://mlsanity.com/paper/2011.04107/) (2020)
- [Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package](https://mlsanity.com/paper/2011.14755/) (2020)

## Abstract (arXiv)

The insatiable appetite of Artificial Intelligence (AI) workloads for computing power is pushing the industry to develop faster and more efficient accelerators. The rigidity of custom hardware, however, conflicts with the need for scalable and versatile architectures capable of catering to the needs of the evolving and heterogeneous pool of Machine Learning (ML) models in the literature. In this context, multi-chiplet architectures assembling multiple (perhaps heterogeneous) accelerators are an appealing option that is unfortunately hindered by the still rigid and inefficient chip-to-chip interconnects. In this paper, we explore the potential of wireless technology as a complement to existing wired interconnects in this multi-chiplet approach. Using an evaluation framework from the state-of-the-art, we show that wireless interconnects can lead to speedups of 10% on average and 20% maximum. We also highlight the importance of load balancing between the wired and wireless interconnects, which will be further explored in future work.