# Flex-PE: Flexible and SIMD Multi-Precision Processing Element for AI Workloads

arXiv: https://arxiv.org/abs/2412.11702 · HTML: https://mlsanity.com/paper/2412.11702/

## Key facts

- Cited by 15 papers in the map (data through 14 Oct 2026).
- Builds on 15 of its 78 references that are in the map.
- First posted on arXiv 16 Dec 2024.

## Builds on (most cited first, 15 of 15)

- [Once-for-All: Train One Network and Specialize it for Efficient Deployment](https://mlsanity.com/paper/1908.09791/) (2019)
- [TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings](https://mlsanity.com/paper/2304.01433/) (2023)
- [Activation Functions in Deep Learning: A Comprehensive Survey and Benchmark](https://mlsanity.com/paper/2109.14545/) (2021)
- [AI and Memory Wall](https://mlsanity.com/paper/2403.14123/) (2024)
- [Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers](https://mlsanity.com/paper/2103.09301/) (2021)
- [NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps](https://mlsanity.com/paper/1706.01406/) (2017)
- [An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs](https://mlsanity.com/paper/2001.01955/) (2020)
- [RAMAN: A Re-configurable and Sparse tinyML Accelerator for Inference on Edge](https://mlsanity.com/paper/2306.06493/) (2023)
- [Ensemble of Convolutional Neural Networks Trained with Different Activation Functions](https://mlsanity.com/paper/1905.02473/) (2019)
- [Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In](https://mlsanity.com/paper/2305.04760/) (2023)
- [ShortcutFusion: From Tensorflow to FPGA-based accelerator with reuse-aware memory allocation for shortcut data](https://mlsanity.com/paper/2106.08167/) (2021)
- [Design Space Exploration of Neural Network Activation Function Circuits](https://mlsanity.com/paper/1810.08650/) (2018)
- [Low-Precision Mixed-Computation Models for Inference on Edge](https://mlsanity.com/paper/2312.02210/) (2023)
- [A Transistor Operations Model for Deep Learning Energy Consumption Scaling Law](https://mlsanity.com/paper/2205.15062/) (2022)
- [LoopTree: Exploring the Fused-layer Dataflow Accelerator Design Space](https://mlsanity.com/paper/2409.13625/) (2024)

## Built on by (most cited first, 15 of 15)

- [POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration](https://mlsanity.com/paper/2506.08785/) (2025)
- [ShadowNPU: System and Algorithm Co-design for NPU-Centric On-Device LLM Inference](https://mlsanity.com/paper/2508.16703/) (2025)
- [XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads](https://mlsanity.com/paper/2508.13049/) (2025)
- [QForce-RL: Quantized FPGA-Optimized Reinforcement Learning Compute Engine](https://mlsanity.com/paper/2506.07046/) (2025)
- [Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework](https://mlsanity.com/paper/2511.06067/) (2025)
- [FERMI-ML: A Flexible and Resource-Efficient Memory-In-Situ SRAM Macro for TinyML acceleration](https://mlsanity.com/paper/2511.12544/) (2025)
- [SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency](https://mlsanity.com/paper/2601.17279/) (2026)
- [Retrospective: A CORDIC Based Configurable Activation Function for NN Applications](https://mlsanity.com/paper/2503.14354/) (2025)
- [Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation](https://mlsanity.com/paper/2510.10676/) (2025)
- [SHIELD8-UAV: Sequential 8-bit Hardware Implementation of a Precision-Aware 1D-F-CNN for Low-Energy UAV Acoustic Detection and Temporal Tracking](https://mlsanity.com/paper/2603.01069/) (2026)
- [L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inference](https://mlsanity.com/paper/2604.03626/) (2026)
- [MATCHA: Efficient Deployment of Deep Neural Networks on Multi-Accelerator Heterogeneous Edge SoCs](https://mlsanity.com/paper/2604.09124/) (2026)
- [EULER-ADAS: Energy-Efficient & SIMD-Unified Logarithmic-Posit Engine for Precision-Reconfigurable Approximate ADAS Acceleration](https://mlsanity.com/paper/2605.06875/) (2026)
- [E-ReCON: An Energy- and Resource-Efficient Precision-Configurable Sparse nvCIM Macro for Conventional and Spiking Neural Edge Inference](https://mlsanity.com/paper/2605.20717/) (2026)
- [SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC](https://mlsanity.com/paper/2606.09946/) (2026)

## Abstract (arXiv)

The rapid adaptation of data driven AI models, such as deep learning inference, training, Vision Transformers (ViTs), and other HPC applications, drives a strong need for runtime precision configurable different non linear activation functions (AF) hardware support. Existing solutions support diverse precision or runtime AF reconfigurability but fail to address both simultaneously. This work proposes a flexible and SIMD multiprecision processing element (FlexPE), which supports diverse runtime configurable AFs, including sigmoid, tanh, ReLU and softmax, and MAC operation. The proposed design achieves an improved throughput of up to 16X FxP4, 8X FxP8, 4X FxP16 and 1X FxP32 in pipeline mode with 100% time multiplexed hardware. This work proposes an area efficient multiprecision iterative mode in the SIMD systolic arrays for edge AI use cases. The design delivers superior performance with up to 62X and 371X reductions in DMA reads for input feature maps and weight filters in VGG16, with an energy efficiency of 8.42 GOPS / W within the accuracy loss of 2%. The proposed architecture supports emerging 4-bit computations for DL inference while enhancing throughput in FxP8/16 modes for transformers and other HPC applications. The proposed approach enables future energy-efficient AI accelerators in edge and cloud environments.