# ML-based AIG Timing Prediction to Enhance Logic Optimization

arXiv: https://arxiv.org/abs/2412.02268 · HTML: https://mlsanity.com/paper/2412.02268/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 3 Dec 2024.

## Built on by (most cited first, 1 of 1)

- [Modeling Relational Logic Circuits for And-Inverter Graph Convolutional Network](https://mlsanity.com/paper/2508.11991/) (2025)

## Abstract (arXiv)

As circuit designs become more intricate, obtaining accurate performance estimation in early stages, for effective design space exploration, becomes more time-consuming. Traditional logic optimization approaches often rely on proxy metrics to approximate post-mapping performance and area. However, these proxies do not always correlate well with actual post-mapping delay and area, resulting in suboptimal designs. To address this issue, we explore a ground-truth-based optimization flow that directly incorporates the exact post-mapping delay and area during optimization. While this approach improves design quality, it also significantly increases computational costs, particularly for large-scale designs. To overcome the runtime challenge, we apply machine learning models to predict post-mapping delay and area using the features extracted from AIGs. Our experimental results show that the model has high prediction accuracy with good generalization to unseen designs. Furthermore, the ML-enhanced logic optimization flow significantly reduces runtime while maintaining comparable performance and area outcomes.