# Instruction Scheduling in the Saturn Vector Unit

arXiv: https://arxiv.org/abs/2412.00997 · HTML: https://mlsanity.com/paper/2412.00997/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 1 Dec 2024.

## Built on by (most cited first, 1 of 1)

- [Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic Programs](https://mlsanity.com/paper/2507.01457/) (2025)

## Abstract (arXiv)

While the challenges and solutions for efficient execution of scalable vector ISAs on long-vector-length microarchitectures have been well established, not all of these solutions are suitable for short-vector-length implementations. This work proposes a novel microarchitecture for instruction sequencing in vector units with short architectural vector lengths. The proposed microarchitecture supports fine-granularity chaining, multi-issue out-of-order execution, zero dead-time, and run-ahead memory accesses with low area or complexity costs. We present the Saturn Vector Unit, a RTL implementation of a RVV vector unit. With our instruction scheduling mechanism, Saturn exhibits comparable or superior power, performance, and area characteristics compared to state-of-the-art long-vector and short-vector implementations.