# Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning

arXiv: https://arxiv.org/abs/2411.15212 · HTML: https://mlsanity.com/paper/2411.15212/

## Key facts

- Cited by 5 papers in the map (data through 14 Oct 2026).
- Builds on 14 of its 33 references that are in the map.
- First posted on arXiv 20 Nov 2024.

## Builds on (most cited first, 14 of 14)

- [Proximal Policy Optimization Algorithms](https://mlsanity.com/paper/1707.06347/) (2017)
- [Semi-Supervised Classification with Graph Convolutional Networks](https://mlsanity.com/paper/1609.02907/) (2016)
- [Neural Message Passing for Quantum Chemistry](https://mlsanity.com/paper/1704.01212/) (2017)
- [Modeling Relational Data with Graph Convolutional Networks](https://mlsanity.com/paper/1703.06103/) (2017)
- [An Introduction to Convolutional Neural Networks](https://mlsanity.com/paper/1511.08458/) (2015)
- [Reinforcement Learning for Combinatorial Optimization: A Survey](https://mlsanity.com/paper/2003.03600/) (2020)
- [A Closer Look at Invalid Action Masking in Policy Gradient Algorithms](https://mlsanity.com/paper/2006.14171/) (2020)
- [Learning to Execute](https://mlsanity.com/paper/1410.4615/) (2014)
- [On Joint Learning for Solving Placement and Routing in Chip Design](https://mlsanity.com/paper/2111.00234/) (2021)
- [MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning](https://mlsanity.com/paper/2211.13382/) (2022)
- [ChiPFormer: Transferable Chip Placement via Offline Decision Transformer](https://mlsanity.com/paper/2306.14744/) (2023)
- [ALIGN: A System for Automating Analog Layout](https://mlsanity.com/paper/2008.10682/) (2020)
- [Fast ML-driven Analog Circuit Layout using Reinforcement Learning and Steiner Trees](https://mlsanity.com/paper/2405.16951/) (2024)
- [Toward Reinforcement Learning-based Rectilinear Macro Placement Under Human Constraints](https://mlsanity.com/paper/2311.03383/) (2023)

## Built on by (most cited first, 5 of 5)

- [Enhancing Reinforcement Learning for the Floorplanning of Analog ICs with Beam Search](https://mlsanity.com/paper/2505.05059/) (2025)
- [OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation](https://mlsanity.com/paper/2601.19439/) (2026)
- [Advancing Routing-Awareness in Analog ICs Floorplanning](https://mlsanity.com/paper/2510.15387/) (2025)
- [Inspector: Conversational and Lightweight Analyzer of Analog Circuit Layouts Using LLM and CNNs](https://mlsanity.com/paper/2609.34976/) (2026)
- [THEIA: A Multimodal Dataset and Benchmark for Vision-Language Analysis of Layout](https://mlsanity.com/paper/2609.35035/) (2026)

## Abstract (arXiv)

Analog integrated circuit (IC) floorplanning is typically a manual process with the placement of components (devices and modules) planned by a layout engineer. This process is further complicated by the interdependence of floorplanning and routing steps, numerous electric and layout-dependent constraints, as well as the high level of customization expected in analog design. This paper presents a novel automatic floorplanning algorithm based on reinforcement learning. It is augmented by a relational graph convolutional neural network model for encoding circuit features and positional constraints. The combination of these two machine learning methods enables knowledge transfer across different circuit designs with distinct topologies and constraints, increasing the generalization ability of the solution. Applied to 6 industrial circuits, our approach surpassed established floorplanning techniques in terms of speed, area and half-perimeter wire length. When integrated into a procedural generator for layout completion, overall layout time was reduced by 67.3% with a 8.3% mean area reduction compared to manual layout.