# Veryl: A New Hardware Description Language as an Altarnative to SystemVerilog

arXiv: https://arxiv.org/abs/2411.12983 · HTML: https://mlsanity.com/paper/2411.12983/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 20 Nov 2024.

## Built on by (most cited first, 1 of 1)

- [OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design](https://mlsanity.com/paper/2606.10285/) (2026)

## Abstract (arXiv)

Veryl, a hardware description language based on SystemVerilog, offers optimized syntax tailored for logic design, ensuring synthesizability and simplifying common constructs. It prioritizes interoperability with SystemVerilog, allowing for smooth integration with existing projects while maintaining high readability. Additionally, Veryl includes a comprehensive set of development support tools, such as package managers and real-time checkers, to boost productivity and streamline the design process. These features empower designers to conduct high-quality hardware design efficiently.