# Increasing the scalability of graph convolution for FPGA-implemented event-based vision

arXiv: https://arxiv.org/abs/2411.04269 · HTML: https://mlsanity.com/paper/2411.04269/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 8 of its 11 references that are in the map.
- First posted on arXiv 6 Nov 2024.

## Builds on (most cited first, 8 of 8)

- [Event-based Vision: A Survey](https://mlsanity.com/paper/1904.08405/) (2019)
- [Recurrent Vision Transformers for Object Detection with Event Cameras](https://mlsanity.com/paper/2212.05598/) (2022)
- [AEGNN: Asynchronous Event-based Graph Neural Networks](https://mlsanity.com/paper/2203.17149/) (2022)
- [Event-Based Angular Velocity Regression with Spiking Networks](https://mlsanity.com/paper/2003.02790/) (2020)
- [EvGNN: An Event-driven Graph Neural Network Accelerator for Edge Vision](https://mlsanity.com/paper/2404.19489/) (2024)
- [A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA](https://mlsanity.com/paper/2401.05626/) (2024)
- [Embedded Graph Convolutional Networks for Real-Time Event Data Processing on SoC FPGAs](https://mlsanity.com/paper/2406.07318/) (2024)
- [Event-based vision on FPGAs -- a survey](https://mlsanity.com/paper/2407.08356/) (2024)

## Built on by (most cited first, 1 of 1)

- [Self-Supervised Event Representations: Towards Accurate, Real-Time Perception on SoC FPGAs](https://mlsanity.com/paper/2505.07556/) (2025)

## Abstract (arXiv)

Event cameras are becoming increasingly popular as an alternative to traditional frame-based vision sensors, especially in mobile robotics. Taking full advantage of their high temporal resolution, high dynamic range, low power consumption and sparsity of event data, which only reflects changes in the observed scene, requires both an efficient algorithm and a specialised hardware platform. A recent trend involves using Graph Convolutional Neural Networks (GCNNs) implemented on a heterogeneous SoC FPGA. In this paper we focus on optimising hardware modules for graph convolution to allow flexible selection of the FPGA resource (BlockRAM, DSP and LUT) for their implementation. We propose a ''two-step convolution'' approach that utilises additional BRAM buffers in order to reduce up to 94% of LUT usage for multiplications. This method significantly improves the scalability of GCNNs, enabling the deployment of models with more layers, larger graphs sizes and their application for more dynamic scenarios.