# RTLRewriter: Methodologies for Large Models aided RTL Code Optimization

arXiv: https://arxiv.org/abs/2409.11414 · HTML: https://mlsanity.com/paper/2409.11414/

## Key facts

- Cited by 31 papers in the map (data through 14 Oct 2026).
- Builds on 20 of its 62 references that are in the map.
- First posted on arXiv 4 Sep 2024.

## Builds on (most cited first, 20 of 20)

- [An Image is Worth 16x16 Words: Transformers for Image Recognition at Scale](https://mlsanity.com/paper/2010.11929/) (2020)
- [GPT-4 Technical Report](https://mlsanity.com/paper/2303.08774/) (2023)
- [Llama 2: Open Foundation and Fine-Tuned Chat Models](https://mlsanity.com/paper/2307.09288/) (2023)
- [Chain-of-Thought Prompting Elicits Reasoning in Large Language Models](https://mlsanity.com/paper/2201.11903/) (2022)
- [XGBoost: A Scalable Tree Boosting System](https://mlsanity.com/paper/1603.02754/) (2016)
- [Lost in the Middle: How Language Models Use Long Contexts](https://mlsanity.com/paper/2307.03172/) (2023)
- [DeepSeek LLM: Scaling Open-Source Language Models with Longtermism](https://mlsanity.com/paper/2401.02954/) (2024)
- [VerilogEval: Evaluating Large Language Models for Verilog Code Generation](https://mlsanity.com/paper/2309.07544/) (2023)
- [VeriGen: A Large Language Model for Verilog Code Generation](https://mlsanity.com/paper/2308.00708/) (2023)
- [ChipNeMo: Domain-Adapted LLMs for Chip Design](https://mlsanity.com/paper/2311.00176/) (2023)
- [Chip-Chat: Challenges and Opportunities in Conversational Hardware Design](https://mlsanity.com/paper/2305.13243/) (2023)
- [ChatEDA: A Large Language Model Powered Autonomous Agent for EDA](https://mlsanity.com/paper/2308.10204/) (2023)
- [RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models](https://mlsanity.com/paper/2311.16543/) (2023)
- [BetterV: Controlled Verilog Generation with Discriminative Guidance](https://mlsanity.com/paper/2402.03375/) (2024)
- [RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution](https://mlsanity.com/paper/2312.08617/) (2023)
- [GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models](https://mlsanity.com/paper/2309.10730/) (2023)
- [Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS](https://mlsanity.com/paper/2402.03289/) (2024)
- [HDLdebugger: Streamlining HDL debugging with Large Language Models](https://mlsanity.com/paper/2403.11671/) (2024)
- [A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design](https://mlsanity.com/paper/2309.03208/) (2023)
- [Logic Synthesis with Generative Deep Neural Networks](https://mlsanity.com/paper/2406.04699/) (2024)

## Built on by (most cited first, 30 of 31)

- [A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA](https://mlsanity.com/paper/2504.03711/) (2025)
- [RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs](https://mlsanity.com/paper/2507.16200/) (2025)
- [VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation](https://mlsanity.com/paper/2504.15659/) (2025)
- [MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization](https://mlsanity.com/paper/2507.19570/) (2025)
- [Revolution or Hype? Seeking the Limits of Large Models in Hardware Design](https://mlsanity.com/paper/2509.04905/) (2025)
- [MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs](https://mlsanity.com/paper/2411.03471/) (2024)
- [EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization](https://mlsanity.com/paper/2601.18067/) (2026)
- [ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection](https://mlsanity.com/paper/2505.19734/) (2025)
- [DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs](https://mlsanity.com/paper/2507.02226/) (2025)
- [ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning](https://mlsanity.com/paper/2507.04736/) (2025)
- [DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning](https://mlsanity.com/paper/2502.06816/) (2025)
- [VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code](https://mlsanity.com/paper/2506.07239/) (2025)
- [CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs](https://mlsanity.com/paper/2507.02128/) (2025)
- [Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code](https://mlsanity.com/paper/2510.14756/) (2025)
- [SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip](https://mlsanity.com/paper/2508.12910/) (2025)
- [AgenticTCAD: A LLM-based Multi-Agent Framework for Automated TCAD Code Generation and Device Optimization](https://mlsanity.com/paper/2512.23742/) (2025)
- [CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization](https://mlsanity.com/paper/2603.17204/) (2026)
- [BRIDGES: Bridging Graph Modality and Large Language Models within EDA Tasks](https://mlsanity.com/paper/2504.05180/) (2025)
- [GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment](https://mlsanity.com/paper/2504.09485/) (2025)
- [Rethinking LLM-Based RTL Code Optimization Via Timing Logic Metamorphosis](https://mlsanity.com/paper/2507.16808/) (2025)
- [Principle-Guided Verilog Optimization: IP-Safe Knowledge Transfer via Local-Cloud Collaboration](https://mlsanity.com/paper/2508.05675/) (2025)
- [CRADLE: Conversational RTL Design Space Exploration with LLM-based Multi-Agent Systems](https://mlsanity.com/paper/2508.08709/) (2025)
- [LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration](https://mlsanity.com/paper/2608.27184/) (2026)
- [GENIAL: Generative Design Space Exploration via Network Inversion for Low Power Algorithmic Logic Units](https://mlsanity.com/paper/2507.18989/) (2025)
- [AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning](https://mlsanity.com/paper/2604.18445/) (2026)
- [Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation](https://mlsanity.com/paper/2605.26498/) (2026)
- [LLM4RTL: Tool-Assisted LLM for RTL Generation](https://mlsanity.com/paper/2606.15500/) (2026)
- [AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting](https://mlsanity.com/paper/2606.17461/) (2026)
- [TicTacBench: Benchmarking Timing Closure Capabilities of Coding Agents](https://mlsanity.com/paper/2609.23363/) (2026)
- [ChipMEM: Verification-Grounded Memory for EDA Agents](https://mlsanity.com/paper/2609.27067/) (2026)

## Abstract (arXiv)

Register Transfer Level (RTL) code optimization is crucial for enhancing the efficiency and performance of digital circuits during early synthesis stages. Currently, optimization relies heavily on manual efforts by skilled engineers, often requiring multiple iterations based on synthesis feedback. In contrast, existing compiler-based methods fall short in addressing complex designs. This paper introduces RTLRewriter, an innovative framework that leverages large models to optimize RTL code. A circuit partition pipeline is utilized for fast synthesis and efficient rewriting. A multi-modal program analysis is proposed to incorporate vital visual diagram information as optimization cues. A specialized search engine is designed to identify useful optimization guides, algorithms, and code snippets that enhance the model ability to generate optimized RTL. Additionally, we introduce a Cost-aware Monte Carlo Tree Search (C-MCTS) algorithm for efficient rewriting, managing diverse retrieved contents and steering the rewriting results. Furthermore, a fast verification pipeline is proposed to reduce verification cost. To cater to the needs of both industry and academia, we propose two benchmarking suites: the Large Rewriter Benchmark, targeting complex scenarios with extensive circuit partitioning, optimization trade-offs, and verification challenges, and the Small Rewriter Benchmark, designed for a wider range of scenarios and patterns. Our comparative analysis with established compilers such as Yosys and E-graph demonstrates significant improvements, highlighting the benefits of integrating large models into the early stages of circuit design. We provide our benchmarks at https://github.com/yaoxufeng/RTLRewriter-Bench.