# Automatic Generation of Fast and Accurate Performance Models for Deep Neural Network Accelerators

arXiv: https://arxiv.org/abs/2409.08595 · HTML: https://mlsanity.com/paper/2409.08595/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 7 of its 33 references that are in the map.
- First posted on arXiv 13 Sep 2024.

## Builds on (most cited first, 7 of 7)

- [EfficientNet: Rethinking Model Scaling for Convolutional Neural Networks](https://mlsanity.com/paper/1905.11946/) (2019)
- [Temporal Convolution for Real-time Keyword Spotting on Mobile Devices](https://mlsanity.com/paper/1904.03814/) (2019)
- [Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Devices](https://mlsanity.com/paper/2209.03807/) (2022)
- [YodaNN: An Architecture for Ultra-Low Power Binary-Weight CNN Acceleration](https://mlsanity.com/paper/1606.05487/) (2016)
- [PreVIous: A Methodology for Prediction of Visual Inference Performance on IoT Devices](https://mlsanity.com/paper/1912.06442/) (2019)
- [ANNETTE: Accurate Neural Network Execution Time Estimation with Stacked Models](https://mlsanity.com/paper/2105.03176/) (2021)
- [Using the Abstract Computer Architecture Description Language to Model AI Hardware Accelerators](https://mlsanity.com/paper/2402.00069/) (2024)

## Abstract (arXiv)

Implementing Deep Neural Networks (DNNs) on resource-constrained edge devices is a challenging task that requires tailored hardware accelerator architectures and a clear understanding of their performance characteristics when executing the intended AI workload. To facilitate this, we present an automated generation approach for fast performance models to accurately estimate the latency of a DNN mapped onto systematically modeled and concisely described accelerator architectures. Using our accelerator architecture description method, we modeled representative DNN accelerators such as Gemmini, UltraTrail, Plasticine-derived, and a parameterizable systolic array. Together with DNN mappings for those modeled architectures, we perform a combined DNN/hardware dependency graph analysis, which enables us, in the best case, to evaluate only 154 loop kernel iterations to estimate the performance for 4.19 billion instructions achieving a significant speedup. We outperform regression and analytical models in terms of mean absolute percentage error (MAPE) compared to simulation results, while being several magnitudes faster than an RTL simulation.