# MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning

arXiv: https://arxiv.org/abs/2407.18110 · HTML: https://mlsanity.com/paper/2407.18110/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- Placed in RL for energy, networks and operations, one of 15 directions in Deep reinforcement learning methods.
- Builds on 9 of its 53 references that are in the map.
- First posted on arXiv 25 Jul 2024.

## Placed in

- Deep reinforcement learning methods / [RL for energy, networks and operations](https://mlsanity.com/deeprl/rl-for-energy-networks-and-operations/)

## Builds on (most cited first, 9 of 9)

- [Deep Reinforcement Learning with Double Q-learning](https://mlsanity.com/paper/1509.06461/) (2015)
- [Chip Placement with Deep Reinforcement Learning](https://mlsanity.com/paper/2004.10746/) (2020)
- [Algorithms for multi-armed bandit problems](https://mlsanity.com/paper/1402.6028/) (2014)
- [DRiLLS: Deep Reinforcement Learning for Logic Synthesis](https://mlsanity.com/paper/1911.04021/) (2019)
- [Developing Synthesis Flows Without Human Knowledge](https://mlsanity.com/paper/1804.05714/) (2018)
- [Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets](https://mlsanity.com/paper/1904.07077/) (2019)
- [NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning](https://mlsanity.com/paper/2107.07044/) (2021)
- [Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach](https://mlsanity.com/paper/1902.00478/) (2019)
- [BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation](https://mlsanity.com/paper/2401.10753/) (2024)

## Built on by (most cited first, 4 of 4)

- [DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning](https://mlsanity.com/paper/2502.06816/) (2025)
- [e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving](https://mlsanity.com/paper/2508.13020/) (2025)
- [Revisit Choice Network for Synthesis and Technology Mapping](https://mlsanity.com/paper/2508.14068/) (2025)
- [TOPCELL: Topology Optimization of Standard Cell via LLMs](https://mlsanity.com/paper/2604.14237/) (2026)

## Abstract (arXiv)

Technology mapping involves mapping logical circuits to a library of cells. Traditionally, the full technology library is used, leading to a large search space and potential overhead. Motivated by randomly sampled technology mapping case studies, we propose MapTune framework that addresses this challenge by utilizing reinforcement learning to make design-specific choices during cell selection. By learning from the environment, MapTune refines the cell selection process, resulting in a reduced search space and potentially improved mapping quality. The effectiveness of MapTune is evaluated on a wide range of benchmarks, different technology libraries and technology mappers. The experimental results demonstrate that MapTune achieves higher mapping accuracy and reducing delay/area across diverse circuit designs, technology libraries and mappers. The paper also discusses the Pareto-Optimal exploration and confirms the perpetual delay-area trade-off. Conducted on benchmark suites ISCAS 85/89, ITC/ISCAS 99, VTR8.0 and EPFL benchmarks, the post-technology mapping and post-sizing quality-of-results (QoR) have been significantly improved, with average Area-Delay Product (ADP) improvement of 22.54% among all different exploration settings in MapTune. The improvements are consistently remained for four different technologies (7nm, 45nm, 130nm, and 180 nm) and two different mappers.