# Towards Efficient Design Verification -- Constrained Random Verification using PyUVM

arXiv: https://arxiv.org/abs/2407.10317 · HTML: https://mlsanity.com/paper/2407.10317/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 6 May 2024.

## Built on by (most cited first, 1 of 1)

- [Optimizing Coverage-Driven Verification Using Machine Learning and PyUVM: A Novel Approach](https://mlsanity.com/paper/2503.11666/) (2025)

## Abstract (arXiv)

Python, as a multi-paradigm language known for its ease of integration with other languages, has gained significant attention among verification engineers recently. A Python-based verification environment capitalizes on open-source frameworks such as PyUVM providing Python-based UVM 1.2 implementation and PyVSC facilitating constrained randomization and functional coverage. These libraries play a pivotal role in expediting test development and hold promise for reducing setup costs. The goal of this paper is to evaluate the effectiveness of PyUVM verification testbenches across various design IPs, aiming for a comprehensive comparison of their features and performance metrics with the established SystemVerilog-UVM methodology.