# Effective Design Verification -- Constrained Random with Python and Cocotb

arXiv: https://arxiv.org/abs/2407.10312 · HTML: https://mlsanity.com/paper/2407.10312/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 2 of its 17 references that are in the map.
- First posted on arXiv 6 May 2024.

## Builds on (most cited first, 2 of 2)

- [Optimizing Design Verification using Machine Learning: Doing better than Random](https://mlsanity.com/paper/1909.13168/) (2019)
- [Optimising Design Verification Using Machine Learning: An Open Source Solution](https://mlsanity.com/paper/2012.02453/) (2020)

## Built on by (most cited first, 1 of 1)

- [ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation](https://mlsanity.com/paper/2508.15940/) (2025)

## Abstract (arXiv)

Being the most widely used language across the world due to its simplicity and with 35 keywords (v3.7), Python attracts both hardware and software engineers. Python-based verification environment leverages open-source libraries such as cocotb and cocotb-coverage that enables interfacing the tesbenches with any available simulator and facilitating constrained randomization, coverage respectively. These libraries significantly ease the development of testbenches and have the potential to reduce the setup cost. The goal of this paper is to assess the effectiveness of a Python-Cocotb verification setup with design IPs and compare its features and performance metrics with the current de-facto hardware verification language i.e., SystemVerilog.