# GOALPlace: Begin with the End in Mind

arXiv: https://arxiv.org/abs/2407.04579 · HTML: https://mlsanity.com/paper/2407.04579/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 3 of its 32 references that are in the map.
- First posted on arXiv 5 Jul 2024.

## Builds on (most cited first, 3 of 3)

- [From Louvain to Leiden: guaranteeing well-connected communities](https://mlsanity.com/paper/1810.08473/) (2018)
- [An Updated Assessment of Reinforcement Learning for Macro Placement](https://mlsanity.com/paper/2302.11014/) (2023)
- [Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview](https://mlsanity.com/paper/2202.13564/) (2022)

## Built on by (most cited first, 1 of 1)

- [Recursive Learning-Based Virtual Buffering for Analytical Global Placement](https://mlsanity.com/paper/2506.17247/) (2025)

## Abstract (arXiv)

Co-optimizing placement with congestion is integral to achieving high-quality designs. This paper presents GOALPlace, a new learning-based general approach to improving placement congestion by controlling cell density. Our method efficiently learns from an EDA tool's post-route optimized results and uses an empirical Bayes technique to adapt this goal/target to a specific placer's solutions, effectively beginning with the end in mind. It enhances correlation with the long-running heuristics of the tool's router and timing-opt engine -- while solving placement globally without expensive incremental congestion estimation and mitigation methods. A statistical analysis with a new hierarchical netlist clustering establishes the importance of density and the potential for an adequate cell density target across placements. Our experiments show that our method, integrated as a demonstration inside an academic GPU-accelerated global placer, consistently produces macro and standard cell placements of superior or comparable quality to commercial tools. Our empirical Bayes methodology also allows a substantial quality improvement over state-of-the-art academic mixed-size placers, achieving up to 10x fewer design rule check (DRC) violations, a 5% decrease in wirelength, and a 30% and 60% reduction in worst and total negative slack (WNS/TNS).