# ONNX-to-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs

arXiv: https://arxiv.org/abs/2406.09078 · HTML: https://mlsanity.com/paper/2406.09078/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 13 Jun 2024.

## Built on by (most cited first, 1 of 1)

- [Engineering FAIR Privacy-preserving Applications that Learn Histories of Disease](https://mlsanity.com/paper/2603.00181/) (2026)

## Abstract (arXiv)

The challenges involved in executing neural networks (NNs) at the edge include providing diversity, flexibility, and sustainability. That implies, for instance, supporting evolving applications and algorithms energy-efficiently. Using hardware or software accelerators can deliver fast and efficient computation of the NNs, while flexibility can be exploited to support long-term adaptivity. Nonetheless, handcrafting an NN for a specific device, despite the possibility of leading to an optimal solution, takes time and experience, and that's why frameworks for hardware accelerators are being developed. This work, starting from a preliminary semi-integrated ONNX-to-hardware toolchain [21], focuses on enabling approximate computing leveraging the distinctive ability of the original toolchain to favor adaptivity. The goal is to allow lightweight adaptable NN inference on FPGAs at the edge.