# Investigating Memory Failure Prediction Across CPU Architectures

arXiv: https://arxiv.org/abs/2406.05354 · HTML: https://mlsanity.com/paper/2406.05354/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 5 of its 41 references that are in the map.
- First posted on arXiv 8 Jun 2024.

## Builds on (most cited first, 5 of 5)

- [Revisiting Deep Learning Models for Tabular Data](https://mlsanity.com/paper/2106.11959/) (2021)
- [Workload-Aware DRAM Error Prediction using Machine Learning](https://mlsanity.com/paper/2003.12448/) (2020)
- [A Case for Transparent Reliability in DRAM Systems](https://mlsanity.com/paper/2204.10378/) (2022)
- [First CE Matters: On the Importance of Long Term Properties on Memory Failure Prediction](https://mlsanity.com/paper/2212.10441/) (2022)
- [Exploring Error Bits for Memory Failure Prediction: An In-Depth Correlative Study](https://mlsanity.com/paper/2312.02855/) (2023)

## Abstract (arXiv)

Large-scale datacenters often experience memory failures, where Uncorrectable Errors (UEs) highlight critical malfunction in Dual Inline Memory Modules (DIMMs). Existing approaches primarily utilize Correctable Errors (CEs) to predict UEs, yet they typically neglect how these errors vary between different CPU architectures, especially in terms of Error Correction Code (ECC) applicability. In this paper, we investigate the correlation between CEs and UEs across different CPU architectures, including X86 and ARM. Our analysis identifies unique patterns of memory failure associated with each processor platform. Leveraging Machine Learning (ML) techniques on production datasets, we conduct the memory failure prediction in different processors' platforms, achieving up to 15% improvements in F1-score compared to the existing algorithm. Finally, an MLOps (Machine Learning Operations) framework is provided to consistently improve the failure prediction in the production environment.