# Logic Synthesis with Generative Deep Neural Networks

arXiv: https://arxiv.org/abs/2406.04699 · HTML: https://mlsanity.com/paper/2406.04699/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- Builds on 5 of its 23 references that are in the map.
- First posted on arXiv 7 Jun 2024.

## Builds on (most cited first, 5 of 5)

- [Attention Is All You Need](https://mlsanity.com/paper/1706.03762/) (2017)
- [ChipNeMo: Domain-Adapted LLMs for Chip Design](https://mlsanity.com/paper/2311.00176/) (2023)
- [Chip-Chat: Challenges and Opportunities in Conversational Hardware Design](https://mlsanity.com/paper/2305.13243/) (2023)
- [Machine Learning for Electronic Design Automation: A Survey](https://mlsanity.com/paper/2102.03357/) (2021)
- [DRiLLS: Deep Reinforcement Learning for Logic Synthesis](https://mlsanity.com/paper/1911.04021/) (2019)

## Built on by (most cited first, 4 of 4)

- [RTLRewriter: Methodologies for Large Models aided RTL Code Optimization](https://mlsanity.com/paper/2409.11414/) (2024)
- [SeaDAG: Semi-autoregressive Diffusion for Conditional Directed Acyclic Graph Generation](https://mlsanity.com/paper/2410.16119/) (2024)
- [GENIAL: Generative Design Space Exploration via Network Inversion for Low Power Algorithmic Logic Units](https://mlsanity.com/paper/2507.18989/) (2025)
- [GTAC: A Generative Transformer for Approximate Circuits](https://mlsanity.com/paper/2601.19906/) (2025)

## Abstract (arXiv)

While deep learning has achieved significant success in various domains, its application to logic circuit design has been limited due to complex constraints and strict feasibility requirement. However, a recent generative deep neural model, "Circuit Transformer", has shown promise in this area by enabling equivalence-preserving circuit transformation on a small scale. In this paper, we introduce a logic synthesis rewriting operator based on the Circuit Transformer model, named "ctrw" (Circuit Transformer Rewriting), which incorporates the following techniques: (1) a two-stage training scheme for the Circuit Transformer tailored for logic synthesis, with iterative improvement of optimality through self-improvement training; (2) integration of the Circuit Transformer with state-of-the-art rewriting techniques to address scalability issues, allowing for guided DAG-aware rewriting. Experimental results on the IWLS 2023 contest benchmark demonstrate the effectiveness of our proposed rewriting methods.