# Analog or Digital In-memory Computing? Benchmarking through Quantitative Modeling

arXiv: https://arxiv.org/abs/2405.14978 · HTML: https://mlsanity.com/paper/2405.14978/

## Key facts

- Cited by 7 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 23 May 2024.

## Built on by (most cited first, 7 of 7)

- [MINIMALIST: switched-capacitor circuits for efficient in-memory computation of gated recurrent units](https://mlsanity.com/paper/2505.08599/) (2025)
- [PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation](https://mlsanity.com/paper/2408.16246/) (2024)
- [Compute SNR-Optimal Analog-to-Digital Converters for Analog In-Memory Computing](https://mlsanity.com/paper/2507.09776/) (2025)
- [Efficient Deployment of CNN Models on Multiple In-Memory Computing Units](https://mlsanity.com/paper/2511.04682/) (2025)
- [From RISC-V Cores to Neuromorphic Arrays: A Tutorial on Building Scalable Digital Neuromorphic Processors](https://mlsanity.com/paper/2512.00113/) (2025)
- [Investigating Energy Bounds of Analog Compute-in-Memory with Local Normalization](https://mlsanity.com/paper/2602.08081/) (2026)
- [You Only Charge Once 2.0 : A End-to-End Analog Computing-in-Memory Architecture with Reconfigurable Switched Capacitors](https://mlsanity.com/paper/2608.11116/) (2026)

## Abstract (arXiv)

In-Memory Computing (IMC) has emerged as a promising paradigm for energy-efficient, throughput-efficient and area-efficient machine learning at the edge. However, the differences in hardware architectures, array dimensions, and fabrication technologies among published IMC realizations have made it difficult to grasp their relative strengths. Moreover, previous studies have primarily focused on exploring and benchmarking the peak performance of a single IMC macro rather than full system performance on real workloads. This paper aims to address the lack of a quantitative comparison of Analog In-Memory Computing (AIMC) and Digital In-Memory Computing (DIMC) processor architectures. We propose an analytical IMC performance model that is validated against published implementations and integrated into a system-level exploration framework for comprehensive performance assessments on different workloads with varying IMC configurations. Our experiments show that while DIMC generally has higher computational density than AIMC, AIMC with large macro sizes may have better energy efficiency than DIMC on convolutional-layers and pointwise-layers, which can exploit high spatial unrolling. On the other hand, DIMC with small macro size outperforms AIMC on depthwise-layers, which feature limited spatial unrolling opportunities inside a macro.