# Enabling full-speed random access to the entire memory on the A100 GPU

arXiv: https://arxiv.org/abs/2405.11425 · HTML: https://mlsanity.com/paper/2405.11425/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 19 May 2024.

## Built on by (most cited first, 1 of 1)

- [PLASMA: A Layout-Aware Benchmark Reveals Memory Layout Matters for Graph-based ANNS on GPU](https://mlsanity.com/paper/2508.15436/) (2025)

## Abstract (arXiv)

We describe some features of the A100 memory architecture. In particular, we give a technique to reverse-engineer some hardware layout information. Using this information, we show how to avoid TLB issues to obtain full-speed random HBM access to the entire memory, as long as we constrain any particular thread to a reduced access window of less than 64GB.