# AMSNet: Netlist Dataset for AMS Circuits

arXiv: https://arxiv.org/abs/2405.09045 · HTML: https://mlsanity.com/paper/2405.09045/

## Key facts

- Cited by 25 papers in the map (data through 14 Oct 2026).
- Builds on 6 of its 25 references that are in the map.
- First posted on arXiv 15 May 2024.

## Builds on (most cited first, 6 of 6)

- [RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model](https://mlsanity.com/paper/2308.05345/) (2023)
- [Chip-Chat: Challenges and Opportunities in Conversational Hardware Design](https://mlsanity.com/paper/2305.13243/) (2023)
- [ChatEDA: A Large Language Model Powered Autonomous Agent for EDA](https://mlsanity.com/paper/2308.10204/) (2023)
- [RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution](https://mlsanity.com/paper/2312.08617/) (2023)
- [GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models](https://mlsanity.com/paper/2309.10730/) (2023)
- [KATO: Knowledge Alignment and Transfer for Transistor Sizing of Different Design and Technology](https://mlsanity.com/paper/2404.14433/) (2024)

## Built on by (most cited first, 25 of 25)

- [AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-Design Using Knowledge Graph RAG](https://mlsanity.com/paper/2411.13560/) (2024)
- [AMSbench: A Comprehensive Benchmark for Evaluating MLLM Capabilities in AMS Circuits](https://mlsanity.com/paper/2505.24138/) (2025)
- [AMSnet 2.0: A Large AMS Database with AI Segmentation for Net Detection](https://mlsanity.com/paper/2505.09155/) (2025)
- [MuaLLM: A Multimodal Large Language Model Agent for Circuit Design Assistance with Hybrid Contextual Retrieval-Augmented Generation](https://mlsanity.com/paper/2508.08137/) (2025)
- [SPICED: Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detection](https://mlsanity.com/paper/2408.16018/) (2024)
- [Image2Net: Datasets, Benchmark and Hybrid Framework to Convert Analog Circuit Diagrams into Netlists](https://mlsanity.com/paper/2508.13157/) (2025)
- [TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits](https://mlsanity.com/paper/2509.14169/) (2025)
- [Are LLMs Any Good for High-Level Synthesis?](https://mlsanity.com/paper/2408.10428/) (2024)
- [A Large Language Model-based Multi-Agent Framework for Analog Circuits' Sizing Relationships Extraction](https://mlsanity.com/paper/2506.18424/) (2025)
- [OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation](https://mlsanity.com/paper/2601.19439/) (2026)
- [OmniSch: A Multimodal PCB Schematic Benchmark For Structured Diagram Visual Reasoning](https://mlsanity.com/paper/2604.00270/) (2026)
- [Dataset Construction for Training LLM to Learn Analog Circuit Knowledge](https://mlsanity.com/paper/2508.10409/) (2025)
- [AnalogRetriever: Learning Cross-Modal Representations for Analog Circuit Retrieval](https://mlsanity.com/paper/2604.23195/) (2026)
- [SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows](https://mlsanity.com/paper/2607.03701/) (2026)
- [D2S-FLOW: Automated Parameter Extraction from Datasheets for SPICE Model Generation Using Large Language Models](https://mlsanity.com/paper/2502.16540/) (2025)
- [VLM-CAD: VLM-Optimized Collaborative Agent Design Workflow for Analog Circuit Sizing](https://mlsanity.com/paper/2601.07315/) (2026)
- [DiagramNet: An End-to-End Recognition Framework and Dataset for Non-Standard System-Level Diagrams](https://mlsanity.com/paper/2605.01338/) (2026)
- [AMSnet-q: Unsupervised Circuit Identification and Performance Labeling for AMS Circuits](https://mlsanity.com/paper/2605.01404/) (2026)
- [SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence](https://mlsanity.com/paper/2607.01609/) (2026)
- [EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models](https://mlsanity.com/paper/2607.13416/) (2026)
- [Towards Reliable AI-Assisted Analog Design: Template-Constrained LLM Agents for SAR ADC Generation](https://mlsanity.com/paper/2607.14165/) (2026)
- [ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits](https://mlsanity.com/paper/2607.23225/) (2026)
- [PCBnet: A Dataset and Automatic Construction of SPICE Netlists from Schematic Images](https://mlsanity.com/paper/2608.27923/) (2026)
- [Long-Horizon Analog Design Bench: Benchmarking Agents on Hours-Long Analog and Mixed-Signal Circuit Design Tasks](https://mlsanity.com/paper/2609.33356/) (2026)
- [SGAnalog: An End-to-End Circuit Benchmark from Open-Source Silicon Tapeouts](https://mlsanity.com/paper/2610.03934/) (2026)

## Abstract (arXiv)

Today's analog/mixed-signal (AMS) integrated circuit (IC) designs demand substantial manual intervention. The advent of multimodal large language models (MLLMs) has unveiled significant potential across various fields, suggesting their applicability in streamlining large-scale AMS IC design as well. A bottleneck in employing MLLMs for automatic AMS circuit generation is the absence of a comprehensive dataset delineating the schematic-netlist relationship. We therefore design an automatic technique for converting schematics into netlists, and create dataset AMSNet, encompassing transistor-level schematics and corresponding SPICE format netlists. With a growing size, AMSNet can significantly facilitate exploration of MLLM applications in AMS circuit design. We have made an initial set of netlists public, and will make both our netlist generation tool and the full dataset available upon publishing of this paper.